module branch_comp (
    input [31:0] a,
    input [31:0] b,
    input BrUn,
    output BrEq,
    output BrLt
);
    // wire [32:0] comp_a, comp_b;
    // assign comp_a = (BrUn) ? {1'b0, a} : $signed({1'b1, a});
    // assign comp_b = (BrUn) ? {1'b0, b} : $signed({1'b1, b});
    // assign BrEq = (comp_a == comp_b) ? 1'b1 : 1'b0;
    // assign BrLt = (comp_a < comp_b)  ? 1'b1 : 1'b0;
    
    reg [31:0] eq_out, lt_out;
    always @(*) begin
        case (BrUn)
            1'b1: begin
                eq_out = $unsigned(a) == $unsigned(b);
                lt_out = $unsigned(a) <  $unsigned(b);
            end
            1'b0: begin
                eq_out = $signed(a) == $signed(b);
                lt_out = $signed(a) <  $signed(b);
            end
        endcase
    end
    assign BrEq = eq_out;
    assign BrLt = lt_out;
endmodule