module f_ex_pipeline (
    input clk,
    input rst,
    input [31:0] f_pc,
    input [31:0] f_inst,
    input [31:0] f_rd1,
    input [31:0] f_rd2,
    output [31:0] ex_pc,
    output [31:0] ex_inst,
    output [31:0] ex_rd1,
    output [31:0] ex_rd2
);

    reg [31:0] ex_pc_reg;
    reg [31:0] ex_inst_reg;
    reg [31:0] ex_rd1_reg;
    reg [31:0] ex_rd2_reg;
    always @(posedge clk) begin
        if (rst) begin
            ex_pc_reg <= 32'd0;
            ex_inst_reg <= 32'd0;
            ex_rd1_reg <= 31'd0;
            ex_rd2_reg <= 31'd0;
        end else begin
            ex_pc_reg <= f_pc;
            ex_inst_reg <= f_inst;
            ex_rd1_reg <= f_rd1;
            ex_rd2_reg <= f_rd2;
        end
    end
    assign ex_pc = ex_pc_reg;
    assign ex_inst = ex_inst_reg;
    assign ex_rd1 = ex_rd1_reg;
    assign ex_rd2 = ex_rd2_reg;

endmodule

module ex_wb_pipeline (
    input clk,
    input rst,
    input [31:0] ex_pc,
    input [31:0] ex_inst,
    input ex_PCSel,
    input [1:0] ex_WBSel,
    input ex_RegWEn,
    input [31:0] ex_alu,
    output [31:0] wb_pc,
    output [31:0] wb_inst,
    output wb_PCSel,
    output [1:0] wb_WBSel,
    output wb_RegWEn,
    output [31:0] wb_alu
);

    
    reg [31:0] wb_pc_reg;
    reg [31:0] wb_inst_reg;
    reg wb_PCSel_reg;
    reg [1:0] wb_WBSel_reg;
    reg wb_RegWEn_reg;
    reg [31:0] wb_alu_reg;
    always @(posedge clk) begin
        if (rst) begin
            wb_pc_reg <= 32'd0;
            wb_inst_reg <= 32'd0;
            wb_PCSel_reg <= 1'd0;
            wb_WBSel_reg <= 2'd0;
            wb_RegWEn_reg <= 1'd0;
            wb_alu_reg <= 32'd0;
        end else begin
            wb_pc_reg <= ex_pc;
            wb_inst_reg <= ex_inst;
            wb_PCSel_reg <= ex_PCSel;
            wb_WBSel_reg <= ex_WBSel;
            wb_RegWEn_reg <= ex_RegWEn;
            wb_alu_reg <= ex_alu;
        end
    end
    assign wb_pc = wb_pc_reg;
    assign wb_inst = wb_inst_reg;
    assign wb_PCSel = wb_PCSel_reg;
    assign wb_WBSel = wb_WBSel_reg;
    assign wb_RegWEn = wb_RegWEn_reg;
    assign wb_alu = wb_alu_reg;

endmodule

module fd_ex_pipe (
    input clk, rst,
    input [31:0] fd_pc, fd_inst,
    input [31:0] fd_imm, fd_rd1, fd_rd2,
    input fd_ASel, fd_BSel,
    input [3:0] fd_ALUSel, fd_MemRW,
    output [31:0] ex_pc, ex_inst,
    output [31:0] ex_imm, ex_rd1, ex_rd2,
    output ex_ASel, ex_BSel,
    output [3:0] ex_ALUSel, ex_MemRW
);

    reg [31:0] ex_pc_out, ex_inst_out;
    reg [31:0] ex_imm_out, ex_rd1_out, ex_rd2_out;
    reg ex_ASel_out, ex_BSel_out;
    reg [3:0] ex_ALUSel_out, ex_MemRW_out;
    always @(posedge clk) begin
        if (rst) begin
            ex_pc_out <= 32'd0;
            ex_inst_out <= 32'd0;
            ex_imm_out <= 32'd0;
            ex_rd1_out <= 32'd0;
            ex_rd2_out <= 32'd0;
            ex_ASel_out <= 1'd0;
            ex_BSel_out <= 1'd0;
            ex_ALUSel_out <= 4'd0;
            ex_MemRW_out <= 4'd0;
        end else begin
            ex_pc_out <= fd_pc;
            ex_inst_out <= fd_inst;
            ex_imm_out <= fd_imm;
            ex_rd1_out <= fd_rd1;
            ex_rd2_out <= fd_rd2;
            ex_ASel_out <= fd_ASel;
            ex_BSel_out <= fd_BSel;
            ex_ALUSel_out <= fd_ALUSel;
            ex_MemRW_out <= fd_MemRW;
        end
    end
    assign ex_pc = ex_pc_out;
    assign ex_inst = ex_inst_out;
    assign ex_imm = ex_imm_out;
    assign ex_rd1 = ex_rd1_out;
    assign ex_rd2 = ex_rd2_out;
    assign ex_ASel = ex_ASel_out;
    assign ex_BSel = ex_BSel_out;
    assign ex_ALUSel = ex_ALUSel_out;
    assign ex_MemRW = ex_MemRW_out;

endmodule

module ex_wb_pipe (
    input clk, rst,
    input [31:0] ex_pc, ex_inst,
    input [31:0] ex_alu,
    input [1:0] ex_WBSel,
    input ex_RegWEn,
    output [31:0] wb_pc, wb_inst,
    output [31:0] wb_alu,
    output [1:0] wb_WBSel,
    output wb_RegWEn
);
    reg [31:0] wb_pc_out, wb_inst_out;
    reg [31:0] wb_alu_out;
    reg [1:0] wb_WBSel_out;
    reg wb_RegWEn_out;
    always @(posedge clk) begin
        if (rst) begin
            wb_pc_out <= 32'd0;
            wb_inst_out <= 32'd0;
            wb_alu_out <= 32'd0;
            wb_WBSel_out <= 2'd0;
            wb_RegWEn_out <= 1'd0;
        end else begin
            wb_pc_out <= ex_pc;
            wb_inst_out <= ex_inst;
            wb_alu_out <= ex_alu;
            wb_WBSel_out <= ex_WBSel;
            wb_RegWEn_out <= ex_RegWEn;
        end
    end
    assign wb_pc = wb_pc_out;
    assign wb_inst = wb_inst_out;
    assign wb_alu = wb_alu_out;
    assign wb_WBSel = wb_WBSel_out;
    assign wb_RegWEn = wb_RegWEn_out;

endmodule