module reg_file (
    input clk,
    input we,
    input [4:0] ra1, ra2, wa,
    input [31:0] wd,
    output [31:0] rd1, rd2
);
    parameter DEPTH = 32;
    reg [31:0] mem [0:31];

    always @(posedge clk) begin
    if (we)
      mem[wa] <= wd;
    end

    assign rd1 = ((ra1 != 5'd0) ? mem[ra1] : 32'd0);
    assign rd2 = ((ra2 != 5'd0) ? mem[ra2] : 32'd0);
endmodule