hardware/test_results/asm_tb.vpd.out · FPGA-RISC-V-CPU

cd sim && vcs -full64 -notice -line +lint=all,noVCDE,noNS,noSVA-UA -sverilog -timescale=1ns/10ps -debug +define+ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware +incdir+/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core -o asm_tb.tb /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v asm_tb.v -top asm_tb -top glbl

Warning-[LINX_KRNL] Unsupported Linux kernel
  Linux kernel '5.4.206-200.el7.x86_64' is not supported.
  Supported versions are 2.4* or 2.6*.

                         Chronologic VCS (TM)
         Version P-2019.06_Full64 -- Fri Dec  9 07:40:04 2022
               Copyright (c) 1991-2019 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[DEBUG_DEP] Option will be deprecated
  The option 'debug=4' will be deprecated in a future release.  Please use 
  '-debug_acc+pp+f+fn+dmptf -debug_region+cell+encrypt' instead.

Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v'
Parsing design file 'asm_tb.v'
Parsing included file 'mem_path.vh'.
Back to file 'asm_tb.v'.
Top Level Modules:
       glbl
       asm_tb
TimeScale is 1 ps / 1 ps

Lint-[TFIPC-L] Too few instance port connections
asm_tb.v, 14
asm_tb, "cpu #(.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)) cpu( .clk (clk),  .rst (rst),  .serial_in (1'b1));"
  The above instance has fewer port connections than the module definition,
  input port 'bp_enable' is not connected.


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 55
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 9-bit LHS target:
  Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 : 
  (clock_counter + 1));
  Expression: clock_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 61
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= 0;
  Expression: bit_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 63
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= 10;
  Expression: bit_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 65
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= (bit_counter - 1);
  Expression: bit_counter


Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 33
uart_receiver, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
  A left 9-bit expression is compared to a right 32-bit expression.
  Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
  with '(SYMBOL_EDGE_TIME - 1)' of type int.


Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 38
uart_receiver, "(clock_counter == SAMPLE_TIME)"
  A left 9-bit expression is compared to a right 32-bit expression.
  Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
  with 'SAMPLE_TIME' of type int.


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 27
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 9-bit LHS target:
  Source info: clock_counter = 0;
  Expression: clock_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 28
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter = 0;
  Expression: bit_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 45
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 9-bit LHS target:
  Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 : 
  (clock_counter + 1));
  Expression: clock_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 51
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= 0;
  Expression: bit_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 53
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= 10;
  Expression: bit_counter


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 55
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 4-bit LHS target:
  Source info: bit_counter <= (bit_counter - 1);
  Expression: bit_counter


Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 32
uart_transmitter, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
  A left 9-bit expression is compared to a right 32-bit expression.
  Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
  with '(SYMBOL_EDGE_TIME - 1)' of type int.


Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v, 11
  Following variable has never been set any value.
  Source info: mem


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 18
  Width mismatch between LHS and RHS is found in assignment:
  The following 1-bit wide expression is assigned to a 32-bit LHS target:
  Source info: eq_out = ($unsigned(a) == $unsigned(b));
  Expression: eq_out


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 19
  Width mismatch between LHS and RHS is found in assignment:
  The following 1-bit wide expression is assigned to a 32-bit LHS target:
  Source info: lt_out = ($unsigned(a) < $unsigned(b));
  Expression: lt_out


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 22
  Width mismatch between LHS and RHS is found in assignment:
  The following 1-bit wide expression is assigned to a 32-bit LHS target:
  Source info: eq_out = ($signed(a) == $signed(b));
  Expression: eq_out


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 23
  Width mismatch between LHS and RHS is found in assignment:
  The following 1-bit wide expression is assigned to a 32-bit LHS target:
  Source info: lt_out = ($signed(a) < $signed(b));
  Expression: lt_out


Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 27
  Continuous assignment width mismatch
  1 bits (lhs) versus 32 bits (rhs).
  Source info: assign BrEq = eq_out;  


Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 28
  Continuous assignment width mismatch
  1 bits (lhs) versus 32 bits (rhs).
  Source info: assign BrLt = lt_out;  


Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v, 128
  Following variable has never been set any value.
  Source info: stall


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v, 56
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 8-bit LHS target:
  Source info: is_valid <= 0;
  Expression: is_valid


Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
sat_updn, "(in < ((2 ** WIDTH) - 1))"
  A left 2-bit expression is compared to a right 32-bit expression.
  Comparing 'in' of type wire [(WIDTH - 1):0]
  with '((2 ** WIDTH) - 1)' of type bit signed [31:0].


Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
  Continuous assignment width mismatch
  2 bits (lhs) versus 32 bits (rhs).
  Source info: assign out = ((in + ((up && (in < ((2 ** WIDTH) - 1))) ? 1 : 
  0)) + ((dn && (in > 0)) ? (-1) : 0));  


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 16
  Width mismatch between LHS and RHS is found in assignment:
  The following 16-bit wide expression is assigned to a 32-bit LHS target:
  Source info: out = (din[15:0] << (addr[1:0] * 8));
  Expression: out


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 17
  Width mismatch between LHS and RHS is found in assignment:
  The following 8-bit wide expression is assigned to a 32-bit LHS target:
  Source info: out = (din[7:0] << (addr[1:0] * 8));
  Expression: out


Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 16
  Following variable has never been set any value.
  Source info: p_up_tmp


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 42
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: JTAG_SEL1_GLBL = 0;
  Expression: JTAG_SEL1_GLBL


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 43
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: JTAG_SEL2_GLBL = 0;
  Expression: JTAG_SEL2_GLBL


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 44
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: JTAG_SEL3_GLBL = 0;
  Expression: JTAG_SEL3_GLBL


Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 45
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: JTAG_SEL4_GLBL = 0;
  Expression: JTAG_SEL4_GLBL


Lint-[ZERO] Zero delay in design
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 66
glbl, "TOC_WIDTH"
  Use of #0 may result in incorrect results or inconsistent behavior.


Lint-[WMIA-L] Width mismatch in assignment
asm_tb.v, 9
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: clk = 0;
  Expression: clk


Lint-[WMIA-L] Width mismatch in assignment
asm_tb.v, 54
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: rst = 0;
  Expression: rst


Lint-[WMIA-L] Width mismatch in assignment
asm_tb.v, 57
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: rst = 1;
  Expression: rst


Lint-[WMIA-L] Width mismatch in assignment
asm_tb.v, 60
  Width mismatch between LHS and RHS is found in assignment:
  The following 32-bit wide expression is assigned to a 1-bit LHS target:
  Source info: rst = 0;
  Expression: rst

Starting vcs inline pass...
2 modules and 0 UDP read.
Generating code for _VCSgd_reYIK
Generating code for _VCSgd_WZg7r
Generating code for _VCSgd_qWrI5
recompiling module asm_tb
	However, due to incremental compilation, only 1 module needs to be compiled. 
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../asm_tb.tb ]; then chmod -x ../asm_tb.tb; fi
g++  -o ../asm_tb.tb    -rdynamic  -Wl,-rpath='$ORIGIN'/asm_tb.tb.daidir -Wl,-rpath=./asm_tb.tb.daidir -Wl,-rpath=/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib -L/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib  -Wl,-rpath-link=./   objs/amcQw_d.o   _20962_archive_1.so _prev_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive          /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_save_restore_new.o -ldl  -lc -lm -lpthread -ldl 
../asm_tb.tb up to date
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
CPU time: .553 seconds to compile + .368 seconds to elab + .182 seconds to link
cd sim && ./asm_tb.tb +verbose=1 +vpdfile+asm_tb.vpd |& tee asm_tb.log
Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Dec  9 07:40 2022
Message: From $vcdpluson at time 0 in file asm_tb.v line 48: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to asm_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
PASS - test    1, got:        300 for reg  1
PASS - test    2, got:        500 for reg  1
PASS - test    3, got:        100 for reg  2
ALL ASSEMBLY TESTS PASSED!
$finish called from file "asm_tb.v", line 73.
$finish at simulation time               450000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 450000 ps
CPU Time:      0.350 seconds;       Data structure size:   0.1Mb
Fri Dec  9 07:40:06 2022