cd sim && vcs -full64 -notice -line +lint=all,noVCDE,noNS,noSVA-UA -sverilog -timescale=1ns/10ps -debug +define+ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware +incdir+/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core -o bios_tb.tb /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v bios_tb.v -top bios_tb -top glbl
Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '5.4.206-200.el7.x86_64' is not supported.
Supported versions are 2.4* or 2.6*.
Chronologic VCS (TM)
Version P-2019.06_Full64 -- Fri Dec 9 07:40:33 2022
Copyright (c) 1991-2019 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Warning-[DEBUG_DEP] Option will be deprecated
The option 'debug=4' will be deprecated in a future release. Please use
'-debug_acc+pp+f+fn+dmptf -debug_region+cell+encrypt' instead.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v'
Parsing design file 'bios_tb.v'
Parsing included file '../src/riscv_core/opcode.vh'.
Back to file 'bios_tb.v'.
Parsing included file 'mem_path.vh'.
Back to file 'bios_tb.v'.
Top Level Modules:
glbl
bios_tb
TimeScale is 1 ps / 1 ps
Lint-[TFIPC-L] Too few instance port connections
bios_tb.v, 24
bios_tb, "cpu #(.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ), .RESET_PC(32'h40000000), .BAUD_RATE(BAUD_RATE)) cpu( .clk (clk), .rst (rst), .serial_in (serial_in), .serial_out (serial_out));"
The above instance has fewer port connections than the module definition,
input port 'bp_enable' is not connected.
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 55
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 3-bit LHS target:
Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 :
(clock_counter + 1));
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 61
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 63
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 10;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 65
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= (bit_counter - 1);
Expression: bit_counter
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 33
uart_receiver, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
A left 3-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with '(SYMBOL_EDGE_TIME - 1)' of type int.
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 38
uart_receiver, "(clock_counter == SAMPLE_TIME)"
A left 3-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with 'SAMPLE_TIME' of type int.
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 27
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 3-bit LHS target:
Source info: clock_counter = 0;
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 28
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter = 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 45
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 3-bit LHS target:
Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 :
(clock_counter + 1));
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 51
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 53
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 10;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 55
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= (bit_counter - 1);
Expression: bit_counter
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 32
uart_transmitter, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
A left 3-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with '(SYMBOL_EDGE_TIME - 1)' of type int.
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v, 11
Following variable has never been set any value.
Source info: mem
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 18
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: eq_out = ($unsigned(a) == $unsigned(b));
Expression: eq_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 19
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: lt_out = ($unsigned(a) < $unsigned(b));
Expression: lt_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 22
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: eq_out = ($signed(a) == $signed(b));
Expression: eq_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 23
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: lt_out = ($signed(a) < $signed(b));
Expression: lt_out
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 27
Continuous assignment width mismatch
1 bits (lhs) versus 32 bits (rhs).
Source info: assign BrEq = eq_out;
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 28
Continuous assignment width mismatch
1 bits (lhs) versus 32 bits (rhs).
Source info: assign BrLt = lt_out;
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v, 128
Following variable has never been set any value.
Source info: stall
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v, 56
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 8-bit LHS target:
Source info: is_valid <= 0;
Expression: is_valid
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
sat_updn, "(in < ((2 ** WIDTH) - 1))"
A left 2-bit expression is compared to a right 32-bit expression.
Comparing 'in' of type wire [(WIDTH - 1):0]
with '((2 ** WIDTH) - 1)' of type bit signed [31:0].
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
Continuous assignment width mismatch
2 bits (lhs) versus 32 bits (rhs).
Source info: assign out = ((in + ((up && (in < ((2 ** WIDTH) - 1))) ? 1 :
0)) + ((dn && (in > 0)) ? (-1) : 0));
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 16
Width mismatch between LHS and RHS is found in assignment:
The following 16-bit wide expression is assigned to a 32-bit LHS target:
Source info: out = (din[15:0] << (addr[1:0] * 8));
Expression: out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 17
Width mismatch between LHS and RHS is found in assignment:
The following 8-bit wide expression is assigned to a 32-bit LHS target:
Source info: out = (din[7:0] << (addr[1:0] * 8));
Expression: out
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 16
Following variable has never been set any value.
Source info: p_up_tmp
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 42
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL1_GLBL = 0;
Expression: JTAG_SEL1_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 43
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL2_GLBL = 0;
Expression: JTAG_SEL2_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 44
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL3_GLBL = 0;
Expression: JTAG_SEL3_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 45
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL4_GLBL = 0;
Expression: JTAG_SEL4_GLBL
Lint-[ZERO] Zero delay in design
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 66
glbl, "TOC_WIDTH"
Use of #0 may result in incorrect results or inconsistent behavior.
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 14
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: clk = 0;
Expression: clk
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 106
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 12-bit LHS target:
Source info: IMM[11:0] = 8;
Expression: IMM[11:0]
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 107
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 122
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 1;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 123
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: serial_in = 1;
Expression: serial_in
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 129
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 0;
Expression: rst
Lint-[ULCO] Unequal length in comparison operator
bios_tb.v, 380
bios_tb, "(bios_tb.cpu.rf.mem[3] === IMM[11:0])"
A left 32-bit expression is compared to a right 12-bit expression.
Comparing 'bios_tb.cpu.rf.mem[3]' of type reg [31:0]
with 'IMM[11:0]' of type reg [11:0].
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 45
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: serial_in = 0;
Expression: serial_in
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 53
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: serial_in = 1;
Expression: serial_in
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 82
Width mismatch between LHS and RHS is found in assignment:
The following 48-bit wide expression is assigned to a 64-bit LHS target:
Source info: test_status = "PASSED";
Expression: test_status
Lint-[WMIA-L] Width mismatch in assignment
bios_tb.v, 85
Width mismatch between LHS and RHS is found in assignment:
The following 48-bit wide expression is assigned to a 64-bit LHS target:
Source info: test_status = "FAILED";
Expression: test_status
Starting vcs inline pass...
2 modules and 0 UDP read.
Generating code for _VCSgd_reYIK
Generating code for _VCSgd_WZg7r
Generating code for _VCSgd_DPKe0
recompiling module bios_tb
However, due to incremental compilation, only 1 module needs to be compiled.
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../bios_tb.tb ]; then chmod -x ../bios_tb.tb; fi
g++ -o ../bios_tb.tb -rdynamic -Wl,-rpath='$ORIGIN'/bios_tb.tb.daidir -Wl,-rpath=./bios_tb.tb.daidir -Wl,-rpath=/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib -L/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib -Wl,-rpath-link=./ objs/amcQw_d.o _25111_archive_1.so _prev_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl
../bios_tb.tb up to date
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
CPU time: .672 seconds to compile + .419 seconds to elab + .192 seconds to link
cd sim && ./bios_tb.tb +verbose=1 +vpdfile+bios_tb.vpd |& tee bios_tb.log
Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64; Dec 9 07:40 2022
Message: From $vcdpluson at time 0 in file bios_tb.v line 115: [VCD+-SVFN]:
Setting VPD File by "+vpdfile+" switch to bios_tb.vpd.
VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
[TEST 1] BIOS startup. Expect to see: \r\n151>
[time 2270000, sim. cycle 103] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 3390000, sim. cycle 159] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 4690000, sim. cycle 224] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 5810000, sim. cycle 280] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 6930000, sim. cycle 336] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 8050000, sim. cycle 392] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 9170000, sim. cycle 448] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 2] Send an invalid command. Expect to see: \n\rUnrecognized token:
[time 10170000, sim. cycle 498] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 11850000, sim. cycle 582] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 17150000, sim. cycle 847] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h62
[time 18790000, sim. cycle 929] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h62, expected 8'h62 == b [ PASSED ]
[time 24130000, sim. cycle 1196] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h63
[time 25850000, sim. cycle 1282] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 31110000, sim. cycle 1545] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h64
[time 32790000, sim. cycle 1629] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 38090000, sim. cycle 1894] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 39730000, sim. cycle 1976] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 47270000, sim. cycle 2353] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 48390000, sim. cycle 2409] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 49510000, sim. cycle 2465] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h55, expected 8'h55 == U [ PASSED ]
[time 50630000, sim. cycle 2521] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 51750000, sim. cycle 2577] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h72, expected 8'h72 == r [ PASSED ]
[time 52870000, sim. cycle 2633] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 53990000, sim. cycle 2689] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 55110000, sim. cycle 2745] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6f, expected 8'h6f == o [ PASSED ]
[time 56230000, sim. cycle 2801] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h67, expected 8'h67 == g [ PASSED ]
[time 57350000, sim. cycle 2857] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 58470000, sim. cycle 2913] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h69, expected 8'h69 == i [ PASSED ]
[time 59590000, sim. cycle 2969] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h7a, expected 8'h7a == z [ PASSED ]
[time 60710000, sim. cycle 3025] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 61830000, sim. cycle 3081] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 62950000, sim. cycle 3137] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 64070000, sim. cycle 3193] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h74, expected 8'h74 == t [ PASSED ]
[time 65190000, sim. cycle 3249] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6f, expected 8'h6f == o [ PASSED ]
[time 66310000, sim. cycle 3305] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6b, expected 8'h6b == k [ PASSED ]
[time 67430000, sim. cycle 3361] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 68550000, sim. cycle 3417] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 69670000, sim. cycle 3473] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3a, expected 8'h3a == : [ PASSED ]
[time 70790000, sim. cycle 3529] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 72070000, sim. cycle 3593] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 73190000, sim. cycle 3649] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h62, expected 8'h62 == b [ PASSED ]
[time 74310000, sim. cycle 3705] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 75430000, sim. cycle 3761] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 76730000, sim. cycle 3826] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 77850000, sim. cycle 3882] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 79210000, sim. cycle 3950] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 80330000, sim. cycle 4006] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 81450000, sim. cycle 4062] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 82570000, sim. cycle 4118] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 83690000, sim. cycle 4174] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 3] Send [sw cafeaaaa 30000004] command. Expect to write 32'hcafeaaaa to both IMem[1] and DMem[1]
[time 84690000, sim. cycle 4224] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h73
[time 86370000, sim. cycle 4308] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h73, expected 8'h73 == s [ PASSED ]
[time 91670000, sim. cycle 4573] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h77
[time 93310000, sim. cycle 4655] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h77, expected 8'h77 == w [ PASSED ]
[time 98650000, sim. cycle 4922] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 100370000, sim. cycle 5008] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 105630000, sim. cycle 5271] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h63
[time 107910000, sim. cycle 5385] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 112610000, sim. cycle 5620] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 114250000, sim. cycle 5702] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 119590000, sim. cycle 5969] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h66
[time 121310000, sim. cycle 6055] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h66, expected 8'h66 == f [ PASSED ]
[time 126570000, sim. cycle 6318] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h65
[time 128250000, sim. cycle 6402] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 133550000, sim. cycle 6667] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 135190000, sim. cycle 6749] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 140530000, sim. cycle 7016] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 142250000, sim. cycle 7102] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 147510000, sim. cycle 7365] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 149190000, sim. cycle 7449] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 154490000, sim. cycle 7714] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 156130000, sim. cycle 7796] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 161470000, sim. cycle 8063] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 163190000, sim. cycle 8149] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 168450000, sim. cycle 8412] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h33
[time 175430000, sim. cycle 8761] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 175990000, sim. cycle 8789] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 178370000, sim. cycle 8908] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 182410000, sim. cycle 9110] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 184110000, sim. cycle 9195] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 189390000, sim. cycle 9459] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 191050000, sim. cycle 9542] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 196370000, sim. cycle 9808] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 198110000, sim. cycle 9895] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 203350000, sim. cycle 10157] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 205050000, sim. cycle 10242] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 210330000, sim. cycle 10506] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 211990000, sim. cycle 10589] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 217310000, sim. cycle 10855] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h34
[time 219050000, sim. cycle 10942] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 224290000, sim. cycle 11204] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 226430000, sim. cycle 11311] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 227550000, sim. cycle 11367] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 238910000, sim. cycle 11935] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 240030000, sim. cycle 11991] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 241150000, sim. cycle 12047] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 242270000, sim. cycle 12103] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 243390000, sim. cycle 12159] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
Imem[1]=cafeaaaa DMem[1]=cafeaaaa
Test Write to IMem
PASSED!
Test Write to DMem
PASSED!
[TEST 4] Send [lw 30000004] command. Expect to see: 30000004:cafeaaaa
[time 244390000, sim. cycle 12209] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6c
[time 246070000, sim. cycle 12293] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6c, expected 8'h6c == l [ PASSED ]
[time 251370000, sim. cycle 12558] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h77
[time 253010000, sim. cycle 12640] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h77, expected 8'h77 == w [ PASSED ]
[time 258350000, sim. cycle 12907] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 260070000, sim. cycle 12993] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 265330000, sim. cycle 13256] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h33
[time 267070000, sim. cycle 13343] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 272310000, sim. cycle 13605] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 274010000, sim. cycle 13690] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 279290000, sim. cycle 13954] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 280950000, sim. cycle 14037] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 286270000, sim. cycle 14303] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 288010000, sim. cycle 14390] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 293250000, sim. cycle 14652] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 294950000, sim. cycle 14737] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 300230000, sim. cycle 15001] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 301890000, sim. cycle 15084] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 307210000, sim. cycle 15350] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 308950000, sim. cycle 15437] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 314190000, sim. cycle 15699] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h34
[time 315890000, sim. cycle 15784] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 321170000, sim. cycle 16048] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 323270000, sim. cycle 16153] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 324390000, sim. cycle 16209] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 342250000, sim. cycle 17102] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 343370000, sim. cycle 17158] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 344490000, sim. cycle 17214] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 345610000, sim. cycle 17270] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 346730000, sim. cycle 17326] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 347850000, sim. cycle 17382] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 348970000, sim. cycle 17438] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 350090000, sim. cycle 17494] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 351390000, sim. cycle 17559] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3a, expected 8'h3a == : [ PASSED ]
[time 359830000, sim. cycle 17981] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 360950000, sim. cycle 18037] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 362070000, sim. cycle 18093] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h66, expected 8'h66 == f [ PASSED ]
[time 363190000, sim. cycle 18149] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 364310000, sim. cycle 18205] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 365430000, sim. cycle 18261] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 366550000, sim. cycle 18317] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 367670000, sim. cycle 18373] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 368970000, sim. cycle 18438] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 370090000, sim. cycle 18494] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 371450000, sim. cycle 18562] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 372570000, sim. cycle 18618] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 373690000, sim. cycle 18674] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 374810000, sim. cycle 18730] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 375930000, sim. cycle 18786] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 5] Send [jal 10000000] command. Expect to see: jal 10000000
[time 376930000, sim. cycle 18836] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6a
[time 378610000, sim. cycle 18920] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6a, expected 8'h6a == j [ PASSED ]
[time 383910000, sim. cycle 19185] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 385550000, sim. cycle 19267] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 390890000, sim. cycle 19534] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6c
[time 392610000, sim. cycle 19620] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6c, expected 8'h6c == l [ PASSED ]
[time 397870000, sim. cycle 19883] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 399550000, sim. cycle 19967] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 404850000, sim. cycle 20232] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h31
[time 406530000, sim. cycle 20316] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 411830000, sim. cycle 20581] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 413470000, sim. cycle 20663] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 418810000, sim. cycle 20930] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 420530000, sim. cycle 21016] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 425790000, sim. cycle 21279] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 427470000, sim. cycle 21363] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 432770000, sim. cycle 21628] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 434410000, sim. cycle 21710] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 439750000, sim. cycle 21977] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 441470000, sim. cycle 22063] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 446730000, sim. cycle 22326] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 448410000, sim. cycle 22410] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 453710000, sim. cycle 22675] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 455350000, sim. cycle 22757] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 460690000, sim. cycle 23024] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 462850000, sim. cycle 23132] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
Test RF: RF[3]=00000008
PASSED!
BIOS testbench done! Num failed tests: 0
$finish called from file "bios_tb.v", line 388.
$finish at simulation time 488670000
V C S S i m u l a t i o n R e p o r t
Time: 488670000 ps
CPU Time: 0.710 seconds; Data structure size: 0.3Mb
Fri Dec 9 07:40:36 2022