mkdir -p sim/c_tests
cd sim/c_tests && iverilog -Ttyp -D IVERILOG=1 -g2012 -gassertions -Wall -Wno-timescale -D ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware -I /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core -I /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim -o c_tests_tb.tbi ../c_tests_tb.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/cachetest/cachetest.hex +test_name=cachetest |& tee cachetest.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/cachetest/cachetest.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/cachetest/cachetest.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile cachetest.fst opened for output.
[     20475 sim. cycles] CSR test PASSED!
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/fib/fib.hex +test_name=fib |& tee fib.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/fib/fib.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/fib/fib.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile fib.fst opened for output.
[      1062 sim. cycles] CSR test PASSED!
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/replace/replace.hex +test_name=replace |& tee replace.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/replace/replace.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/replace/replace.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile replace.fst opened for output.
[     13281 sim. cycles] CSR test PASSED!
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/strcmp/strcmp.hex +test_name=strcmp |& tee strcmp.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/strcmp/strcmp.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/strcmp/strcmp.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile strcmp.fst opened for output.
[        93 sim. cycles] CSR test PASSED!
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/sum/sum.hex +test_name=sum |& tee sum.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/sum/sum.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/sum/sum.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile sum.fst opened for output.
[     13269 sim. cycles] CSR test PASSED!
cd sim/c_tests && vvp c_tests_tb.tbi -fst +hex_file=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/vecadd/vecadd.hex +test_name=vecadd |& tee vecadd.log
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/vecadd/vecadd.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/vecadd/vecadd.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile vecadd.fst opened for output.
[     24602 sim. cycles] CSR test PASSED!