cd sim && vcs -full64 -notice -line +lint=all,noVCDE,noNS,noSVA-UA -sverilog -timescale=1ns/10ps -debug +define+ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware +incdir+/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core -o cpu_tb.tb /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v cpu_tb.v -top cpu_tb -top glbl
Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '5.4.206-200.el7.x86_64' is not supported.
Supported versions are 2.4* or 2.6*.
Chronologic VCS (TM)
Version P-2019.06_Full64 -- Fri Dec 9 07:40:00 2022
Copyright (c) 1991-2019 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Warning-[DEBUG_DEP] Option will be deprecated
The option 'debug=4' will be deprecated in a future release. Please use
'-debug_acc+pp+f+fn+dmptf -debug_region+cell+encrypt' instead.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'
Parsing included file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/opcode.vh'.
Back to file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v'.
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v'
Parsing design file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v'
Parsing design file 'cpu_tb.v'
Parsing included file '../src/riscv_core/opcode.vh'.
Back to file 'cpu_tb.v'.
Parsing included file 'mem_path.vh'.
Back to file 'cpu_tb.v'.
Top Level Modules:
glbl
cpu_tb
TimeScale is 1 ps / 1 ps
Lint-[TFIPC-L] Too few instance port connections
cpu_tb.v, 45
cpu_tb, "cpu #(.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ), .RESET_PC(32'h10000000)) cpu( .clk (clk), .rst (rst), .serial_in (1'b1));"
The above instance has fewer port connections than the module definition,
input port 'bp_enable' is not connected.
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 55
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 9-bit LHS target:
Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 :
(clock_counter + 1));
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 61
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 63
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 10;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 65
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= (bit_counter - 1);
Expression: bit_counter
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 33
uart_receiver, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
A left 9-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with '(SYMBOL_EDGE_TIME - 1)' of type int.
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v, 38
uart_receiver, "(clock_counter == SAMPLE_TIME)"
A left 9-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with 'SAMPLE_TIME' of type int.
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 27
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 9-bit LHS target:
Source info: clock_counter = 0;
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 28
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter = 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 45
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 9-bit LHS target:
Source info: clock_counter <= (((start || reset) || symbol_edge) ? 0 :
(clock_counter + 1));
Expression: clock_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 51
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 0;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 53
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= 10;
Expression: bit_counter
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 55
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 4-bit LHS target:
Source info: bit_counter <= (bit_counter - 1);
Expression: bit_counter
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v, 32
uart_transmitter, "(clock_counter == (SYMBOL_EDGE_TIME - 1))"
A left 9-bit expression is compared to a right 32-bit expression.
Comparing 'clock_counter' of type reg [(CLOCK_COUNTER_WIDTH - 1):0]
with '(SYMBOL_EDGE_TIME - 1)' of type int.
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v, 11
Following variable has never been set any value.
Source info: mem
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 18
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: eq_out = ($unsigned(a) == $unsigned(b));
Expression: eq_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 19
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: lt_out = ($unsigned(a) < $unsigned(b));
Expression: lt_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 22
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: eq_out = ($signed(a) == $signed(b));
Expression: eq_out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 23
Width mismatch between LHS and RHS is found in assignment:
The following 1-bit wide expression is assigned to a 32-bit LHS target:
Source info: lt_out = ($signed(a) < $signed(b));
Expression: lt_out
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 27
Continuous assignment width mismatch
1 bits (lhs) versus 32 bits (rhs).
Source info: assign BrEq = eq_out;
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v, 28
Continuous assignment width mismatch
1 bits (lhs) versus 32 bits (rhs).
Source info: assign BrLt = lt_out;
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v, 128
Following variable has never been set any value.
Source info: stall
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v, 56
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 8-bit LHS target:
Source info: is_valid <= 0;
Expression: is_valid
Lint-[ULCO] Unequal length in comparison operator
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
sat_updn, "(in < ((2 ** WIDTH) - 1))"
A left 2-bit expression is compared to a right 32-bit expression.
Comparing 'in' of type wire [(WIDTH - 1):0]
with '((2 ** WIDTH) - 1)' of type bit signed [31:0].
Lint-[CAWM-L] Width mismatch
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v, 16
Continuous assignment width mismatch
2 bits (lhs) versus 32 bits (rhs).
Source info: assign out = ((in + ((up && (in < ((2 ** WIDTH) - 1))) ? 1 :
0)) + ((dn && (in > 0)) ? (-1) : 0));
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 16
Width mismatch between LHS and RHS is found in assignment:
The following 16-bit wide expression is assigned to a 32-bit LHS target:
Source info: out = (din[15:0] << (addr[1:0] * 8));
Expression: out
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v, 17
Width mismatch between LHS and RHS is found in assignment:
The following 8-bit wide expression is assigned to a 32-bit LHS target:
Source info: out = (din[7:0] << (addr[1:0] * 8));
Expression: out
Lint-[VNGS] Variable never gets set
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 16
Following variable has never been set any value.
Source info: p_up_tmp
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 42
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL1_GLBL = 0;
Expression: JTAG_SEL1_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 43
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL2_GLBL = 0;
Expression: JTAG_SEL2_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 44
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL3_GLBL = 0;
Expression: JTAG_SEL3_GLBL
Lint-[WMIA-L] Width mismatch in assignment
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 45
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: JTAG_SEL4_GLBL = 0;
Expression: JTAG_SEL4_GLBL
Lint-[ZERO] Zero delay in design
/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v, 66
glbl, "TOC_WIDTH"
Use of #0 may result in incorrect results or inconsistent behavior.
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 92
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: all_tests_passed = 0;
Expression: all_tests_passed
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 35
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: clk = 0;
Expression: clk
Lint-[ZERO] Zero delay in design
cpu_tb.v, 194
cpu_tb, "0"
Use of #0 may result in incorrect results or inconsistent behavior.
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 195
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 0;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 198
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 1;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 203
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 0;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 211
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 5-bit LHS target:
Source info: RS1 = 1;
Expression: RS1
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 212
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 5-bit LHS target:
Source info: RS2 = 2;
Expression: RS2
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 213
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 5-bit LHS target:
Source info: RD = 3;
Expression: RD
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 217
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 257
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 5-bit LHS target:
Source info: RS1 = 1;
Expression: RS1
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 260
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 286
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 287
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR = ((cpu_tb.cpu.rf.mem[1] + IMM0[11:0]) >> 2);
Expression: DATA_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 359
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 361
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR0 = ((cpu_tb.cpu.rf.mem[2] + IMM0[11:0]) >> 2);
Expression: DATA_ADDR0
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 363
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR1 = ((cpu_tb.cpu.rf.mem[3] + IMM0[11:0]) >> 2);
Expression: DATA_ADDR1
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 364
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR2 = ((cpu_tb.cpu.rf.mem[4] + IMM1[11:0]) >> 2);
Expression: DATA_ADDR2
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 365
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR3 = ((cpu_tb.cpu.rf.mem[5] + IMM2[11:0]) >> 2);
Expression: DATA_ADDR3
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 366
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR4 = ((cpu_tb.cpu.rf.mem[6] + IMM3[11:0]) >> 2);
Expression: DATA_ADDR4
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 368
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR5 = ((cpu_tb.cpu.rf.mem[7] + IMM0[11:0]) >> 2);
Expression: DATA_ADDR5
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 369
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR6 = ((cpu_tb.cpu.rf.mem[8] + IMM1[11:0]) >> 2);
Expression: DATA_ADDR6
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 370
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR7 = ((cpu_tb.cpu.rf.mem[9] + IMM2[11:0]) >> 2);
Expression: DATA_ADDR7
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 371
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR8 = ((cpu_tb.cpu.rf.mem[10] + IMM3[11:0]) >> 2);
Expression: DATA_ADDR8
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 413
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 433
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 455
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 472
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 476
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[0] = "B-Type BEQ Taken 1";
Expression: BR_NAME_TK1[0]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 477
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[0] = "B-Type BEQ Taken 2";
Expression: BR_NAME_TK2[0]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 478
Width mismatch between LHS and RHS is found in assignment:
The following 160-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[0] = "B-Type BEQ Not Taken";
Expression: BR_NAME_NTK[0]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 484
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[1] = "B-Type BNE Taken 1";
Expression: BR_NAME_TK1[1]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 485
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[1] = "B-Type BNE Taken 2";
Expression: BR_NAME_TK2[1]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 486
Width mismatch between LHS and RHS is found in assignment:
The following 160-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[1] = "B-Type BNE Not Taken";
Expression: BR_NAME_NTK[1]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 491
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[2] = "B-Type BLT Taken 1";
Expression: BR_NAME_TK1[2]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 492
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[2] = "B-Type BLT Taken 2";
Expression: BR_NAME_TK2[2]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 493
Width mismatch between LHS and RHS is found in assignment:
The following 160-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[2] = "B-Type BLT Not Taken";
Expression: BR_NAME_NTK[2]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 498
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[3] = "B-Type BGE Taken 1";
Expression: BR_NAME_TK1[3]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 499
Width mismatch between LHS and RHS is found in assignment:
The following 144-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[3] = "B-Type BGE Taken 2";
Expression: BR_NAME_TK2[3]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 500
Width mismatch between LHS and RHS is found in assignment:
The following 160-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[3] = "B-Type BGE Not Taken";
Expression: BR_NAME_NTK[3]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 505
Width mismatch between LHS and RHS is found in assignment:
The following 152-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[4] = "B-Type BLTU Taken 1";
Expression: BR_NAME_TK1[4]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 506
Width mismatch between LHS and RHS is found in assignment:
The following 152-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[4] = "B-Type BLTU Taken 2";
Expression: BR_NAME_TK2[4]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 507
Width mismatch between LHS and RHS is found in assignment:
The following 168-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[4] = "B-Type BLTU Not Taken";
Expression: BR_NAME_NTK[4]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 512
Width mismatch between LHS and RHS is found in assignment:
The following 152-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK1[5] = "B-Type BGEU Taken 1";
Expression: BR_NAME_TK1[5]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 513
Width mismatch between LHS and RHS is found in assignment:
The following 152-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_TK2[5] = "B-Type BGEU Taken 2";
Expression: BR_NAME_TK2[5]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 514
Width mismatch between LHS and RHS is found in assignment:
The following 168-bit wide expression is assigned to a 256-bit LHS target:
Source info: BR_NAME_NTK[5] = "B-Type BGEU Not Taken";
Expression: BR_NAME_NTK[5]
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 556
Width mismatch between LHS and RHS is found in assignment:
The following 5-bit wide expression is assigned to a 32-bit LHS target:
Source info: IMM = 5'd16;
Expression: IMM
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 557
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 565
Width mismatch between LHS and RHS is found in assignment:
The following 80-bit wide expression is assigned to a 256-bit LHS target:
Source info: current_test_type = "CSRRW Test";
Expression: current_test_type
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 566
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 0;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 569
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 1;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 574
Width mismatch between LHS and RHS is found in assignment:
The following 88-bit wide expression is assigned to a 256-bit LHS target:
Source info: current_test_type = "CSRRWI Test";
Expression: current_test_type
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 575
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 0;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 577
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 1;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 585
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 594
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 603
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 613
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 623
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 635
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 636
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR = ((cpu_tb.cpu.rf.mem[4] + IMM[11:0]) >> 2);
Expression: DATA_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 647
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 648
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR = ((cpu_tb.cpu.rf.mem[1] + IMM[11:0]) >> 2);
Expression: DATA_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 661
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 662
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR0 = ((cpu_tb.cpu.rf.mem[1] + IMM[11:0]) >> 2);
Expression: DATA_ADDR0
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 663
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR1 = ((cpu_tb.cpu.rf.mem[4] + IMM[11:0]) >> 2);
Expression: DATA_ADDR1
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 676
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 677
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR0 = ((cpu_tb.cpu.rf.mem[1] + IMM[11:0]) >> 2);
Expression: DATA_ADDR0
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 679
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 15-bit LHS target:
Source info: DATA_ADDR1 = ((cpu_tb.cpu.dmem.mem[DATA_ADDR0] + IMM[11:0]) >>
2);
Expression: DATA_ADDR1
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 689
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 706
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 719
Width mismatch between LHS and RHS is found in assignment:
The following 14-bit wide expression is assigned to a 15-bit LHS target:
Source info: INST_ADDR = 14'b0;
Expression: INST_ADDR
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 72
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 1;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 74
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: rst = 0;
Expression: rst
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 124
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 0;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 133
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 1;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 146
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 0;
Expression: done
Lint-[WMIA-L] Width mismatch in assignment
cpu_tb.v, 155
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: done = 1;
Expression: done
Starting vcs inline pass...
2 modules and 0 UDP read.
Generating code for _VCSgd_reYIK
Generating code for _VCSgd_WZg7r
recompiling module glbl
Generating code for _VCSgd_mvuYT
recompiling module cpu_tb
Both modules done.
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
make[1]: Entering directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../cpu_tb.tb ]; then chmod -x ../cpu_tb.tb; fi
g++ -o ../cpu_tb.tb -rdynamic -Wl,-rpath='$ORIGIN'/cpu_tb.tb.daidir -Wl,-rpath=./cpu_tb.tb.daidir -Wl,-rpath=/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib -L/share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib -Wl,-rpath-link=./ objs/amcQw_d.o _19714_archive_1.so _prev_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /share/instsww/synopsys-new/vcs/P-2019.06/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl
../cpu_tb.tb up to date
make[1]: Leaving directory `/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim/csrc'
CPU time: .795 seconds to compile + .346 seconds to elab + .171 seconds to link
cd sim && ./cpu_tb.tb +verbose=1 +vpdfile+cpu_tb.vpd |& tee cpu_tb.log
Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64; Dec 9 07:40 2022
Message: From $vcdpluson at time 0 in file cpu_tb.v line 187: [VCD+-SVFN]:
Setting VPD File by "+vpdfile+" switch to cpu_tb.vpd.
VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
[ 1] Test R-Type ADD passed!
[ 2] Test R-Type SUB passed!
[ 3] Test R-Type SLL passed!
[ 4] Test R-Type SLT passed!
[ 5] Test R-Type SLTU passed!
[ 6] Test R-Type XOR passed!
[ 7] Test R-Type OR passed!
[ 8] Test R-Type AND passed!
[ 9] Test R-Type SRL passed!
[ 10] Test R-Type SRA passed!
[ 11] Test R-Type SLLI passed!
[ 12] Test R-Type SRLI passed!
[ 13] Test R-Type SRAI passed!
[ 14] Test I-Type ADD passed!
[ 15] Test I-Type SLT passed!
[ 16] Test I-Type SLTU passed!
[ 17] Test I-Type XOR passed!
[ 18] Test I-Type OR passed!
[ 19] Test I-Type AND passed!
[ 20] Test I-Type LW passed!
[ 21] Test I-Type LH 0 passed!
[ 22] Test I-Type LH 2 passed!
[ 23] Test I-Type LB 0 passed!
[ 24] Test I-Type LB 1 passed!
[ 25] Test I-Type LB 2 passed!
[ 26] Test I-Type LB 3 passed!
[ 27] Test I-Type LHU 0 passed!
[ 28] Test I-Type LHU 2 passed!
[ 29] Test I-Type LBU 0 passed!
[ 30] Test I-Type LBU 1 passed!
[ 31] Test I-Type LBU 2 passed!
[ 32] Test I-Type LBU 3 passed!
[ 33] Test S-Type SW passed!
[ 34] Test S-Type SH 1 passed!
[ 35] Test S-Type SH 3 passed!
[ 36] Test S-Type SB 1 passed!
[ 37] Test S-Type SB 2 passed!
[ 38] Test S-Type SB 3 passed!
[ 39] Test S-Type SB 4 passed!
[ 40] Test U-Type LUI passed!
[ 41] Test U-Type AUIPC passed!
[ 42] Test J-Type JAL passed!
[ 43] Test J-Type JAL passed!
[ 44] Test J-Type JAL passed!
[ 45] Test J-Type JALR passed!
[ 46] Test J-Type JALR passed!
[ 47] Test J-Type JALR passed!
[ 48] Test B-Type BEQ Taken 1 passed!
[ 49] Test B-Type BEQ Taken 2 passed!
[ 50] Test B-Type BEQ Not Taken passed!
[ 51] Test B-Type BNE Taken 1 passed!
[ 52] Test B-Type BNE Taken 2 passed!
[ 53] Test B-Type BNE Not Taken passed!
[ 54] Test B-Type BLT Taken 1 passed!
[ 55] Test B-Type BLT Taken 2 passed!
[ 56] Test B-Type BLT Not Taken passed!
[ 57] Test B-Type BGE Taken 1 passed!
[ 58] Test B-Type BGE Taken 2 passed!
[ 59] Test B-Type BGE Not Taken passed!
[ 60] Test B-Type BLTU Taken 1 passed!
[ 61] Test B-Type BLTU Taken 2 passed!
[ 62] Test B-Type BLTU Not Taken passed!
[ 63] Test B-Type BGEU Taken 1 passed!
[ 64] Test B-Type BGEU Taken 2 passed!
[ 65] Test B-Type BGEU Not Taken passed!
[ 66] Test CSRRW passed!
[ 67] Test CSRRWI passed!
[ 68] Test Hazard 1 passed!
[ 69] Test Hazard 2 passed!
[ 70] Test Hazard 3 passed!
[ 71] Test Hazard 4 passed!
[ 72] Test Hazard 5 passed!
[ 73] Test Hazard 6 passed!
[ 74] Test Hazard 7 passed!
[ 75] Test Hazard 8 passed!
[ 76] Test Hazard 9 passed!
[ 77] Test Hazard 10 1 passed!
[ 78] Test Hazard 10 2 passed!
[ 79] Test Hazard 11 passed!
[ 80] Test Hazard 12 passed!
All tests passed!
$finish called from file "cpu_tb.v", line 732.
$finish at simulation time 7210000
V C S S i m u l a t i o n R e p o r t
Time: 7210000 ps
CPU Time: 0.420 seconds; Data structure size: 0.3Mb
Fri Dec 9 07:40:03 2022