FPGA-RISC-V-CPU / hardware / vivado.log
vivado.log
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#-----------------------------------------------------------
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Fri Dec  9 08:15:12 2022
# Process ID: 26398
# Current directory: /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware
# Command line: vivado
# Log file: /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/vivado.log
# Journal file: /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/vivado.jou
#-----------------------------------------------------------
start_gui
open_checkpoint /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/z1top_routed.dcp
Command: open_checkpoint /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/z1top_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.05 . Memory (MB): peak = 7537.816 ; gain = 0.000 ; free physical = 3612 ; free virtual = 13490
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share/instsww/xilinx/Vivado/2021.1/data/ip'.
INFO: [Device 21-403] Loading part xc7z020clg400-1
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 7560.996 ; gain = 0.000 ; free physical = 3211 ; free virtual = 13069
INFO: [Netlist 29-17] Analyzing 182 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.31 . Memory (MB): peak = 7812.711 ; gain = 5.938 ; free physical = 2674 ; free virtual = 12529
Restored from archive | CPU: 0.310000 secs | Memory: 4.633400 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.31 . Memory (MB): peak = 7812.711 ; gain = 5.938 ; free physical = 2674 ; free virtual = 12529
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7812.711 ; gain = 0.000 ; free physical = 2674 ; free virtual = 12529
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 43 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32(x2)): 28 instances
  RAM16X1D => RAM32X1S (RAMS32): 1 instance 
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2021.1 (64-bit) build 3247384
open_checkpoint: Time (s): cpu = 00:00:46 ; elapsed = 00:00:29 . Memory (MB): peak = 8002.199 ; gain = 464.383 ; free physical = 2532 ; free virtual = 12397
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
exit
INFO: [Common 17-206] Exiting Vivado at Fri Dec  9 08:17:50 2022...
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