# EECS 151/251A FPGA Project Skeleton for Fall 2022

This is the RISC-V processor designed by Leonard Wei and Ryan Ma for EECS 151LB in Fall 2022. You can find all individual modules for the CPU in [/hardware/src/](/hardware/src/) and all the testbenches in [/hardware/sim/](/hardware/sim/). You can read our final report [here](EECS151_Final_Report.pdf). The rest of this README is the original README from the skeleton code.

## Specs

Please see ***[/spec/EECS151_FPGA_Project_Fa22.pdf](https://github.com/EECS150/fpga_project_skeleton_fa22/blob/master/spec/EECS151_FPGA_Project_Fa22.pdf)*** for the specifications. Click "More Pages" at the bottom to see the complete pdf.

## Deadlines

**Checkpoint 1:** 3-stage RISC-V (rv32ui) Processor Block Design Diagram & Questions

**Checkpoint 2:** Fully functional 3-stage RISC-V (rv32ui) Processor

**Checkpoint 3:** Branch Predictor using Branch History Table

**Checkpoint 4:** Processor Optimization


## Resources:

RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Hardware for Machine Learning: https://inst.eecs.berkeley.edu//~ee290-2

MIT Eyeriss Tutorial: http://eyeriss.mit.edu/tutorial.html

FPGA Labs FA22: https://github.com/EECS150/fpga_labs_fa22