Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
| Date         : Fri Dec  9 08:07:48 2022
| Host         : c111-4.eecs.berkeley.edu running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command      : report_timing_summary -warn_on_violation -file post_route_timing_summary.rpt
| Design       : z1top
| Device       : 7z020-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
----------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (3)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (3)
------------------------------
 There are 3 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.393        0.000                      0                 2860        0.075        0.000                      0                 2860        2.000        0.000                       0                   748  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                 Waveform(ns)         Period(ns)      Frequency(MHz)
-----                 ------------         ----------      --------------
CLK_125MHZ_FPGA       {0.000 4.000}        8.000           125.000         
  cpu_clk_int         {0.000 10.000}       20.000          50.000          
  cpu_clk_pll_fb_out  {0.000 20.000}       40.000          25.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
CLK_125MHZ_FPGA                                                                                                                                                         2.000        0.000                       0                     1  
  cpu_clk_int               1.393        0.000                      0                 2860        0.075        0.000                      0                 2860        8.750        0.000                       0                   744  
  cpu_clk_pll_fb_out                                                                                                                                                   12.633        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  CLK_125MHZ_FPGA
  To Clock:  CLK_125MHZ_FPGA

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLK_125MHZ_FPGA
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { CLK_125MHZ_FPGA }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         8.000       6.751      PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        8.000       44.633     PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000      PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000      PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  cpu_clk_int
  To Clock:  cpu_clk_int

Setup :            0  Failing Endpoints,  Worst Slack        1.393ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.075ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        8.750ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.393ns  (required time - arrival time)
  Source:                 cpu/dmem/mem_reg_1_3/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            cpu/imem/mem_reg_3_1/WEA[0]
                            (rising edge-triggered cell RAMB36E1 clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             cpu_clk_int
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (cpu_clk_int rise@20.000ns - cpu_clk_int rise@0.000ns)
  Data Path Delay:        17.624ns  (logic 4.705ns (26.697%)  route 12.919ns (73.303%))
  Logic Levels:           16  (CARRY4=3 LUT3=2 LUT4=2 LUT5=1 LUT6=8)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns = ( 22.424 - 20.000 ) 
    Source Clock Delay      (SCD):    2.529ns
    Clock Pessimism Removal (CPR):    -0.004ns
  Clock Uncertainty:      0.141ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.273ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         1.451     1.451 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=1, routed)           1.306     2.757    clk_gen/clk_125mhz
    PLLE2_ADV_X1Y2       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -4.306    -1.549 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, routed)           2.200     0.651    clk_gen/cpu_clk_int
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     0.752 r  clk_gen/cpu_clk_buf/O
                         net (fo=742, routed)         1.777     2.529    cpu/dmem/cpu_clk
    RAMB36_X1Y4          RAMB36E1                                     r  cpu/dmem/mem_reg_1_3/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y4          RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[0])
                                                      2.454     4.983 r  cpu/dmem/mem_reg_1_3/DOADO[0]
                         net (fo=1, routed)           1.593     6.576    cpu/bios_mem/dout[14]
    SLICE_X32Y10         LUT6 (Prop_lut6_I5_O)        0.124     6.700 r  cpu/bios_mem/mem_reg_r1_0_31_6_11_i_46/O
                         net (fo=1, routed)           1.316     8.016    cpu/bios_mem/mem_reg_r1_0_31_6_11_i_46_n_0
    SLICE_X49Y9          LUT6 (Prop_lut6_I5_O)        0.124     8.140 r  cpu/bios_mem/mem_reg_r1_0_31_6_11_i_27/O
                         net (fo=3, routed)           1.003     9.143    cpu/bios_mem/mem_reg_r1_0_31_6_11_i_27_n_0
    SLICE_X43Y10         LUT6 (Prop_lut6_I1_O)        0.124     9.267 r  cpu/bios_mem/mem_reg_r1_0_31_12_17_i_17/O
                         net (fo=1, routed)           0.553     9.819    cpu/bios_mem/mem_reg_r1_0_31_12_17_i_17_n_0
    SLICE_X43Y6          LUT6 (Prop_lut6_I3_O)        0.124     9.943 r  cpu/bios_mem/mem_reg_r1_0_31_12_17_i_4/O
                         net (fo=6, routed)           0.586    10.530    cpu/bios_mem/wb_mux[14]
    SLICE_X44Y5          LUT3 (Prop_lut3_I0_O)        0.124    10.654 r  cpu/bios_mem/mem_reg_1_3_i_4/O
                         net (fo=10, routed)          0.566    11.220    cpu/bios_mem/fwd_b[14]
    SLICE_X49Y7          LUT3 (Prop_lut3_I2_O)        0.124    11.344 r  cpu/bios_mem/mem_reg_0_0_i_112/O
                         net (fo=8, routed)           0.869    12.213    cpu/bios_mem/b_mux[14]
    SLICE_X46Y12         LUT4 (Prop_lut4_I1_O)        0.124    12.337 r  cpu/bios_mem/wb_alu[0]_i_52/O
                         net (fo=2, routed)           0.669    13.005    cpu/bios_mem/wb_alu[0]_i_52_n_0
    SLICE_X47Y12         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    13.390 r  cpu/bios_mem/wb_alu_reg[0]_i_37/CO[3]
                         net (fo=1, routed)           0.000    13.390    cpu/bios_mem/wb_alu_reg[0]_i_37_n_0
    SLICE_X47Y13         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    13.504 r  cpu/bios_mem/wb_alu_reg[0]_i_19/CO[3]
                         net (fo=1, routed)           0.000    13.504    cpu/bios_mem/wb_alu_reg[0]_i_19_n_0
    SLICE_X47Y14         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    13.618 r  cpu/bios_mem/wb_alu_reg[0]_i_17/CO[3]
                         net (fo=1, routed)           1.001    14.620    cpu/bios_mem/alu/data3
    SLICE_X49Y15         LUT5 (Prop_lut5_I0_O)        0.124    14.744 r  cpu/bios_mem/wb_alu[0]_i_14/O
                         net (fo=1, routed)           0.609    15.352    cpu/bios_mem/wb_alu[0]_i_14_n_0
    SLICE_X53Y12         LUT6 (Prop_lut6_I2_O)        0.124    15.476 r  cpu/bios_mem/wb_alu[0]_i_5/O
                         net (fo=2, routed)           0.421    15.898    cpu/bios_mem/wb_alu[0]_i_5_n_0
    SLICE_X53Y12         LUT6 (Prop_lut6_I5_O)        0.124    16.022 r  cpu/bios_mem/wb_alu[0]_i_1/O
                         net (fo=10, routed)          0.877    16.898    cpu/bios_mem/ex_alu[0]
    SLICE_X39Y13         LUT6 (Prop_lut6_I0_O)        0.124    17.022 r  cpu/bios_mem/mem_reg_1_0_i_8/O
                         net (fo=3, routed)           0.375    17.397    cpu/bios_mem/mem_reg_1_0_i_8_n_0
    SLICE_X39Y13         LUT6 (Prop_lut6_I0_O)        0.124    17.521 r  cpu/bios_mem/mem_reg_3_0_i_9/O
                         net (fo=2, routed)           0.592    18.113    cpu/bios_mem/mem_reg_3_0_i_9_n_0
    SLICE_X41Y14         LUT4 (Prop_lut4_I3_O)        0.150    18.263 r  cpu/bios_mem/mem_reg_3_0_i_1__0/O
                         net (fo=4, routed)           1.889    20.153    cpu/imem/imem_wea[3]
    RAMB36_X4Y3          RAMB36E1                                     r  cpu/imem/mem_reg_3_1/WEA[0]
  -------------------------------------------------------------------    -------------------

                         (clock cpu_clk_int rise edge)
                                                     20.000    20.000 r  
    H16                                               0.000    20.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000    20.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         1.380    21.380 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=1, routed)           1.181    22.561    clk_gen/clk_125mhz
    PLLE2_ADV_X1Y2       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -3.890    18.671 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, routed)           2.007    20.678    clk_gen/cpu_clk_int
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    20.769 r  clk_gen/cpu_clk_buf/O
                         net (fo=742, routed)         1.655    22.424    cpu/imem/cpu_clk
    RAMB36_X4Y3          RAMB36E1                                     r  cpu/imem/mem_reg_3_1/CLKARDCLK
                         clock pessimism             -0.004    22.421    
                         clock uncertainty           -0.141    22.279    
    RAMB36_X4Y3          RAMB36E1 (Setup_ramb36e1_CLKARDCLK_WEA[0])
                                                     -0.734    21.545    cpu/imem/mem_reg_3_1
  -------------------------------------------------------------------
                         required time                         21.545    
                         arrival time                         -20.153    
  -------------------------------------------------------------------
                         slack                                  1.393    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.075ns  (arrival time - required time)
  Source:                 cpu/f_ex_pc_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            cpu/ex_wb_pc_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             cpu_clk_int
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (cpu_clk_int rise@0.000ns - cpu_clk_int rise@0.000ns)
  Data Path Delay:        0.406ns  (logic 0.141ns (34.696%)  route 0.265ns (65.304%))
  Logic Levels:           0  
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.765ns
    Source Clock Delay      (SCD):    0.539ns
    Clock Pessimism Removal (CPR):    -0.040ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         0.219     0.219 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.659    clk_gen/clk_125mhz
    PLLE2_ADV_X1Y2       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -1.415    -0.756 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, routed)           0.711    -0.044    clk_gen/cpu_clk_int
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -0.018 r  clk_gen/cpu_clk_buf/O
                         net (fo=742, routed)         0.558     0.539    cpu/cpu_clk
    SLICE_X52Y4          FDRE                                         r  cpu/f_ex_pc_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y4          FDRE (Prop_fdre_C_Q)         0.141     0.680 r  cpu/f_ex_pc_reg[12]/Q
                         net (fo=5, routed)           0.265     0.946    cpu/f_ex_pc_reg_n_0_[12]
    SLICE_X48Y7          FDRE                                         r  cpu/ex_wb_pc_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         0.406     0.406 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=1, routed)           0.481     0.887    clk_gen/clk_125mhz
    PLLE2_ADV_X1Y2       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -1.747    -0.860 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, routed)           0.768    -0.092    clk_gen/cpu_clk_int
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -0.063 r  clk_gen/cpu_clk_buf/O
                         net (fo=742, routed)         0.828     0.765    cpu/cpu_clk
    SLICE_X48Y7          FDRE                                         r  cpu/ex_wb_pc_reg[12]/C
                         clock pessimism              0.040     0.805    
    SLICE_X48Y7          FDRE (Hold_fdre_C_D)         0.066     0.871    cpu/ex_wb_pc_reg[12]
  -------------------------------------------------------------------
                         required time                         -0.871    
                         arrival time                           0.946    
  -------------------------------------------------------------------
                         slack                                  0.075    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         cpu_clk_int
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clk_gen/plle2_cpu_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         20.000      17.056     RAMB36_X3Y0     cpu/imem/mem_reg_0_0/CLKARDCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0   n/a            160.000       20.000      140.000    PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKOUT0
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         10.000      8.750      SLICE_X42Y7     cpu/br_pred/cache/data_reg_0_7_0_0/SP/CLK
High Pulse Width  Slow    RAMS32/CLK          n/a            1.250         10.000      8.750      SLICE_X42Y7     cpu/br_pred/cache/data_reg_0_7_0_0/SP/CLK



---------------------------------------------------------------------------------------------------
From Clock:  cpu_clk_pll_fb_out
  To Clock:  cpu_clk_pll_fb_out

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       12.633ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         cpu_clk_pll_fb_out
Waveform(ns):       { 0.000 20.000 }
Period(ns):         40.000
Sources:            { clk_gen/plle2_cpu_inst/CLKFBOUT }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I             n/a            2.155         40.000      37.845     BUFGCTRL_X0Y17  clk_gen/cpu_clk_f_buf/I
Max Period  n/a     PLLE2_ADV/CLKFBIN  n/a            52.633        40.000      12.633     PLLE2_ADV_X1Y2  clk_gen/plle2_cpu_inst/CLKFBIN



