Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3247384
date_generatedFri Dec 9 08:08:13 2022 os_platformLIN64
product_versionVivado v2021.1 (64-bit) project_id08ee37da3dbc4bca9f33ded9a04d64fa
project_iteration1 random_id8dedbe9220ec504db315f8139ef10657
registration_id8dedbe9220ec504db315f8139ef10657 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-3470T CPU @ 2.90GHz cpu_speed1699.727 MHz
os_nameCentOS os_releaseCentOS Linux release 7.9.2009 (Core)
system_ram16.000 GB total_processors1

vivado_usage
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=[unknown]
default_library=xil_defaultlib designmode=GateLvl export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=0 synthesisstrategy=[unknown]
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=0

unisim_transformation
post_unisim_transformation
bufg=4 carry4=104 fdre=543 fdse=2
gnd=14 ibuf=4 lut1=11 lut2=128
lut3=185 lut4=297 lut5=269 lut6=740
obuf=3 obuft=6 plle2_adv=2 ramb36e1=34
ramd32=126 rams32=20 vcc=13
pre_unisim_transformation
bufg=4 carry4=104 fdre=543 fdse=2
gnd=13 ibuf=4 lut1=11 lut2=128
lut3=185 lut4=297 lut5=269 lut6=740
obuf=3 obuft=6 plle2_adv=2 ram16x1d=29
ram32m=10 ram32x1d=4 ramb36e1=34 vcc=13

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=68 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=545 srls_augmented=0
srls_newly_gated=0 srls_total=0

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=0.49 secs
usage_count
qor_summary=2

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
plio-8=1 zps7-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=2
bufgctrl_util_percentage=6.25 bufhce_available=72 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=0 bufhce_util_percentage=0.00 bufio_available=16 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=8
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_prohibited=0
mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00 plle2_adv_available=4 plle2_adv_fixed=0
plle2_adv_prohibited=0 plle2_adv_used=1 plle2_adv_util_percentage=25.00
dsp
dsps_available=220 dsps_fixed=0 dsps_prohibited=0 dsps_used=0
dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=34
block_ram_tile_util_percentage=24.29 ramb18_available=280 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=0 ramb18_util_percentage=0.00 ramb36_fifo_available=140 ramb36_fifo_fixed=0
ramb36_fifo_prohibited=0 ramb36_fifo_used=34 ramb36_fifo_util_percentage=24.29 ramb36e1_only_used=34
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=104
fdre_functional_category=Flop & Latch fdre_used=543 fdse_functional_category=Flop & Latch fdse_used=2
ibuf_functional_category=IO ibuf_used=4 lut1_functional_category=LUT lut1_used=11
lut2_functional_category=LUT lut2_used=128 lut3_functional_category=LUT lut3_used=185
lut4_functional_category=LUT lut4_used=297 lut5_functional_category=LUT lut5_used=269
lut6_functional_category=LUT lut6_used=740 obuf_functional_category=IO obuf_used=3
obuft_functional_category=IO obuft_used=6 plle2_adv_functional_category=Clock plle2_adv_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=34 ramd32_functional_category=Distributed Memory ramd32_used=124
rams32_functional_category=Distributed Memory rams32_used=21
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=0
f7_muxes_util_percentage=0.00 f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=73
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=1413
lut_as_logic_util_percentage=2.66 lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=73 lut_as_memory_util_percentage=0.42 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0 register_as_flip_flop_used=543
register_as_flip_flop_util_percentage=0.51 register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_prohibited=0
register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=53200 slice_luts_fixed=0
slice_luts_prohibited=0 slice_luts_used=1486 slice_luts_util_percentage=2.79 slice_registers_available=106400
slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=543 slice_registers_util_percentage=0.51
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=73 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=1413 lut_as_logic_util_percentage=2.66 lut_as_memory_available=17400
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=73 lut_as_memory_util_percentage=0.42
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_in_front_of_the_register_is_unused_available=0 lut_in_front_of_the_register_is_unused_fixed=0
lut_in_front_of_the_register_is_unused_prohibited=0 lut_in_front_of_the_register_is_unused_used=53 lut_in_front_of_the_register_is_used_available=53 lut_in_front_of_the_register_is_used_fixed=53
lut_in_front_of_the_register_is_used_prohibited=53 lut_in_front_of_the_register_is_used_used=168 register_driven_from_outside_the_slice_fixed=168 register_driven_from_outside_the_slice_used=221
register_driven_from_within_the_slice_fixed=221 register_driven_from_within_the_slice_used=322 slice_available=13300 slice_fixed=0
slice_prohibited=0 slice_registers_available=106400 slice_registers_fixed=0 slice_registers_prohibited=0
slice_registers_used=543 slice_registers_util_percentage=0.51 slice_used=469 slice_util_percentage=3.53
slicel_fixed=0 slicel_used=320 slicem_fixed=0 slicem_used=149
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_prohibited=0 unique_control_sets_used=16
unique_control_sets_util_percentage=0.12 using_o5_and_o6_available=0.12 using_o5_and_o6_fixed=0.12 using_o5_and_o6_prohibited=0.12
using_o5_and_o6_used=72 using_o5_output_only_available=72 using_o5_output_only_fixed=72 using_o5_output_only_prohibited=72
using_o5_output_only_used=1 using_o6_output_only_available=1 using_o6_output_only_fixed=1 using_o6_output_only_prohibited=1
using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=0
bscane2_util_percentage=0.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 startupe2_available=1 startupe2_fixed=0
startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00 xadc_available=1
xadc_fixed=0 xadc_prohibited=0 xadc_used=0 xadc_util_percentage=0.00