Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
| Date         : Fri Dec  9 08:05:42 2022
| Host         : c111-4.eecs.berkeley.edu running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command      : report_timing_summary -file post_synth_timing_summary.rpt
| Design       : z1top
| Device       : 7z020-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
----------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (3)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (3)
------------------------------
 There are 3 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      3.946        0.000                      0                 2865        0.085        0.000                      0                 2865        2.000        0.000                       0                   755  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                 Waveform(ns)         Period(ns)      Frequency(MHz)
-----                 ------------         ----------      --------------
CLK_125MHZ_FPGA       {0.000 4.000}        8.000           125.000         
  cpu_clk_int         {0.000 10.000}       20.000          50.000          
  cpu_clk_pll_fb_out  {0.000 20.000}       40.000          25.000          
  pwm_clk_int         {0.000 3.333}        6.667           150.000         
  pwm_clk_pll_fb_out  {0.000 20.000}       40.000          25.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
CLK_125MHZ_FPGA                                                                                                                                                         2.000        0.000                       0                     2  
  cpu_clk_int               3.946        0.000                      0                 2865        0.085        0.000                      0                 2865        8.750        0.000                       0                   745  
  cpu_clk_pll_fb_out                                                                                                                                                   12.633        0.000                       0                     3  
  pwm_clk_int                                                                                                                                                           4.511        0.000                       0                     2  
  pwm_clk_pll_fb_out                                                                                                                                                   12.633        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  CLK_125MHZ_FPGA
  To Clock:  CLK_125MHZ_FPGA

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLK_125MHZ_FPGA
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { CLK_125MHZ_FPGA }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         8.000       6.751                clk_gen/plle2_cpu_inst/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        8.000       44.633               clk_gen/plle2_cpu_inst/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000                clk_gen/plle2_cpu_inst/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.000       2.000                clk_gen/plle2_cpu_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  cpu_clk_int
  To Clock:  cpu_clk_int

Setup :            0  Failing Endpoints,  Worst Slack        3.946ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.085ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        8.750ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.946ns  (required time - arrival time)
  Source:                 cpu/dmem/mem_reg_2_2/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            cpu/on_chip_uart/uatransmit/clock_counter_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             cpu_clk_int
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (cpu_clk_int rise@20.000ns - cpu_clk_int rise@0.000ns)
  Data Path Delay:        15.211ns  (logic 4.587ns (30.156%)  route 10.624ns (69.844%))
  Logic Levels:           15  (CARRY4=2 LUT3=2 LUT4=3 LUT5=1 LUT6=7)
  Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.035ns = ( 22.035 - 20.000 ) 
    Source Clock Delay      (SCD):    2.250ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.141ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.273ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         1.451     1.451 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=2, unplaced)         0.584     2.035    clk_gen/clk_125mhz
                         PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -1.485     0.550 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, unplaced)         0.800     1.350    clk_gen/cpu_clk_int
                         BUFG (Prop_bufg_I_O)         0.101     1.451 r  clk_gen/cpu_clk_buf/O
                         net (fo=743, unplaced)       0.800     2.250    cpu/dmem/cpu_clk
                         RAMB36E1                                     r  cpu/dmem/mem_reg_2_2/CLKARDCLK
  -------------------------------------------------------------------    -------------------
                         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[0])
                                                      2.454     4.704 r  cpu/dmem/mem_reg_2_2/DOADO[0]
                         net (fo=2, unplaced)         0.800     5.504    cpu/bios_mem/dout[20]
                         LUT6 (Prop_lut6_I5_O)        0.124     5.628 r  cpu/bios_mem/mem_reg_r1_0_31_12_17_i_31/O
                         net (fo=2, unplaced)         0.913     6.541    cpu/bios_mem/mem_reg_r1_0_31_12_17_i_31_n_0
                         LUT4 (Prop_lut4_I0_O)        0.124     6.665 r  cpu/bios_mem/mem_reg_r1_0_31_12_17_i_24/O
                         net (fo=2, unplaced)         0.913     7.578    cpu/bios_mem/mem_reg_r1_0_31_12_17_i_24_n_0
                         LUT6 (Prop_lut6_I1_O)        0.124     7.702 r  cpu/bios_mem/mem_reg_r1_0_31_18_23_i_13/O
                         net (fo=1, unplaced)         0.902     8.604    cpu/bios_mem/mem_reg_r1_0_31_18_23_i_13_n_0
                         LUT6 (Prop_lut6_I1_O)        0.124     8.728 r  cpu/bios_mem/mem_reg_r1_0_31_18_23_i_4/O
                         net (fo=6, unplaced)         0.481     9.209    cpu/bios_mem/wb_mux[20]
                         LUT3 (Prop_lut3_I0_O)        0.124     9.333 r  cpu/bios_mem/mem_reg_2_2_i_8/O
                         net (fo=8, unplaced)         0.487     9.820    cpu/bios_mem/fwd_b[20]
                         LUT3 (Prop_lut3_I2_O)        0.124     9.944 r  cpu/bios_mem/wb_alu[20]_i_5/O
                         net (fo=7, unplaced)         0.937    10.881    cpu/bios_mem/b_mux[20]
                         LUT4 (Prop_lut4_I1_O)        0.124    11.005 r  cpu/bios_mem/wb_alu[0]_i_39/O
                         net (fo=2, unplaced)         0.485    11.490    cpu/bios_mem/wb_alu[0]_i_39_n_0
                         CARRY4 (Prop_carry4_DI[2]_CO[3])
                                                      0.404    11.894 r  cpu/bios_mem/wb_alu_reg[0]_i_28/CO[3]
                         net (fo=1, unplaced)         0.000    11.894    cpu/bios_mem/wb_alu_reg[0]_i_28_n_0
                         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    12.011 f  cpu/bios_mem/wb_alu_reg[0]_i_18/CO[3]
                         net (fo=1, unplaced)         0.918    12.929    cpu/bios_mem/alu/data2
                         LUT5 (Prop_lut5_I1_O)        0.124    13.053 f  cpu/bios_mem/wb_alu[0]_i_14/O
                         net (fo=1, unplaced)         0.449    13.502    cpu/bios_mem/wb_alu[0]_i_14_n_0
                         LUT6 (Prop_lut6_I2_O)        0.124    13.626 f  cpu/bios_mem/wb_alu[0]_i_5/O
                         net (fo=2, unplaced)         0.460    14.086    cpu/bios_mem/wb_alu[0]_i_5_n_0
                         LUT6 (Prop_lut6_I4_O)        0.124    14.210 f  cpu/bios_mem/bit_counter[3]_i_13/O
                         net (fo=1, unplaced)         1.111    15.321    cpu/bios_mem/bit_counter[3]_i_13_n_0
                         LUT6 (Prop_lut6_I2_O)        0.124    15.445 f  cpu/bios_mem/bit_counter[3]_i_5/O
                         net (fo=1, unplaced)         0.449    15.894    cpu/bios_mem/bit_counter[3]_i_5_n_0
                         LUT6 (Prop_lut6_I0_O)        0.124    16.018 r  cpu/bios_mem/bit_counter[3]_i_4/O
                         net (fo=15, unplaced)        0.502    16.520    cpu/bios_mem/start
                         LUT4 (Prop_lut4_I2_O)        0.124    16.644 r  cpu/bios_mem/clock_counter[8]_i_1/O
                         net (fo=9, unplaced)         0.817    17.461    cpu/on_chip_uart/uatransmit/SR[0]
                         FDRE                                         r  cpu/on_chip_uart/uatransmit/clock_counter_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock cpu_clk_int rise edge)
                                                     20.000    20.000 r  
    H16                                               0.000    20.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000    20.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         1.380    21.380 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=2, unplaced)         0.439    21.819    clk_gen/clk_125mhz
                         PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -1.290    20.530 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, unplaced)         0.760    21.289    clk_gen/cpu_clk_int
                         BUFG (Prop_bufg_I_O)         0.091    21.380 r  clk_gen/cpu_clk_buf/O
                         net (fo=743, unplaced)       0.655    22.035    cpu/on_chip_uart/uatransmit/cpu_clk
                         FDRE                                         r  cpu/on_chip_uart/uatransmit/clock_counter_reg[0]/C
                         clock pessimism              0.070    22.105    
                         clock uncertainty           -0.141    21.964    
                         FDRE (Setup_fdre_C_R)       -0.557    21.407    cpu/on_chip_uart/uatransmit/clock_counter_reg[0]
  -------------------------------------------------------------------
                         required time                         21.407    
                         arrival time                         -17.461    
  -------------------------------------------------------------------
                         slack                                  3.946    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.085ns  (arrival time - required time)
  Source:                 cpu/ex_wb_pc_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            cpu/br_pred/cache/tag_reg_0_7_0_0/SP/I
                            (rising edge-triggered cell RAMD32 clocked by cpu_clk_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             cpu_clk_int
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (cpu_clk_int rise@0.000ns - cpu_clk_int rise@0.000ns)
  Data Path Delay:        0.298ns  (logic 0.147ns (49.345%)  route 0.151ns (50.655%))
  Logic Levels:           0  
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.761ns
    Source Clock Delay      (SCD):    0.429ns
    Clock Pessimism Removal (CPR):    0.188ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         0.219     0.219 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=2, unplaced)         0.114     0.333    clk_gen/clk_125mhz
                         PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -0.477    -0.144 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, unplaced)         0.337     0.193    clk_gen/cpu_clk_int
                         BUFG (Prop_bufg_I_O)         0.026     0.219 r  clk_gen/cpu_clk_buf/O
                         net (fo=743, unplaced)       0.210     0.429    cpu/cpu_clk
                         FDRE                                         r  cpu/ex_wb_pc_reg[5]/C
  -------------------------------------------------------------------    -------------------
                         FDRE (Prop_fdre_C_Q)         0.147     0.576 r  cpu/ex_wb_pc_reg[5]/Q
                         net (fo=4, unplaced)         0.151     0.727    cpu/br_pred/cache/tag_reg_0_7_0_0/D
                         RAMD32                                       r  cpu/br_pred/cache/tag_reg_0_7_0_0/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock cpu_clk_int rise edge)
                                                      0.000     0.000 r  
    H16                                               0.000     0.000 r  CLK_125MHZ_FPGA (IN)
                         net (fo=0)                   0.000     0.000    CLK_125MHZ_FPGA
    H16                  IBUF (Prop_ibuf_I_O)         0.406     0.406 r  CLK_125MHZ_FPGA_IBUF_inst/O
                         net (fo=2, unplaced)         0.259     0.665    clk_gen/clk_125mhz
                         PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -0.643     0.023 r  clk_gen/plle2_cpu_inst/CLKOUT0
                         net (fo=1, unplaced)         0.355     0.377    clk_gen/cpu_clk_int
                         BUFG (Prop_bufg_I_O)         0.029     0.406 r  clk_gen/cpu_clk_buf/O
                         net (fo=743, unplaced)       0.355     0.761    cpu/br_pred/cache/tag_reg_0_7_0_0/WCLK
                         RAMD32                                       r  cpu/br_pred/cache/tag_reg_0_7_0_0/SP/CLK
                         clock pessimism             -0.188     0.574    
                         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.068     0.642    cpu/br_pred/cache/tag_reg_0_7_0_0/SP
  -------------------------------------------------------------------
                         required time                         -0.642    
                         arrival time                           0.727    
  -------------------------------------------------------------------
                         slack                                  0.085    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         cpu_clk_int
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clk_gen/plle2_cpu_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         20.000      17.056               cpu/imem/mem_reg_0_0/CLKARDCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0   n/a            160.000       20.000      140.000              clk_gen/plle2_cpu_inst/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         10.000      8.750                cpu/br_pred/cache/data_reg_0_7_0_0/DP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         10.000      8.750                cpu/br_pred/cache/data_reg_0_7_0_0/DP/CLK



---------------------------------------------------------------------------------------------------
From Clock:  cpu_clk_pll_fb_out
  To Clock:  cpu_clk_pll_fb_out

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       12.633ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         cpu_clk_pll_fb_out
Waveform(ns):       { 0.000 20.000 }
Period(ns):         40.000
Sources:            { clk_gen/plle2_cpu_inst/CLKFBOUT }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period  n/a     BUFG/I             n/a            2.155         40.000      37.845               clk_gen/cpu_clk_f_buf/I
Max Period  n/a     PLLE2_ADV/CLKFBIN  n/a            52.633        40.000      12.633               clk_gen/plle2_cpu_inst/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pwm_clk_int
  To Clock:  pwm_clk_int

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        4.511ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pwm_clk_int
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk_gen/plle2_pwm_inst/CLKOUT0 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period  n/a     BUFG/I             n/a            2.155         6.667       4.511                clk_gen/pwm_clk_buf/I
Max Period  n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       6.667       153.333              clk_gen/plle2_pwm_inst/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  pwm_clk_pll_fb_out
  To Clock:  pwm_clk_pll_fb_out

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       12.633ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pwm_clk_pll_fb_out
Waveform(ns):       { 0.000 20.000 }
Period(ns):         40.000
Sources:            { clk_gen/plle2_pwm_inst/CLKFBOUT }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period  n/a     BUFG/I             n/a            2.155         40.000      37.845               clk_gen/pwm_clk_f_buf/I
Max Period  n/a     PLLE2_ADV/CLKFBIN  n/a            52.633        40.000      12.633               clk_gen/plle2_pwm_inst/CLKFBIN



