LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PG_CARRY_BLOCK IS
  PORT (
    Ai, Bi, Ci: IN STD_LOGIC;
    Pi, Gi: OUT STD_LOGIC
  );
END ENTITY;
    
ARCHITECTURE BEHAVIORAL OF PG_CARRY_BLOCK IS
BEGIN
    Pi <= Ai XOR Bi XOR Ci;
    Gi <= (Ai AND Bi) OR (Ai AND Ci) OR (Bi AND Ci);
END ARCHITECTURE;