DLX-Microprocessor / components / pg_network_block.vhd
pg_network_block.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PG_NETWORK_BLOCK IS
  PORT (
    Ai, Bi: IN STD_LOGIC;
    Pi, Gi: OUT STD_LOGIC
  );
END ENTITY;
    
ARCHITECTURE BEHAVIORAL OF PG_NETWORK_BLOCK IS
BEGIN
    Pi <= Ai XOR Bi;
    Gi <= Ai AND Bi;
END ARCHITECTURE;