DLX-Microprocessor / physical_design / constraints / dlx-synthesized_constraints-verystrictopt.sdc
dlx-synthesized_constraints-verystrictopt.sdc
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# Created by write_sdc on Fri Jul 18 23:07:03 2025

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set sdc_version 2.1

set_units -time ns -resistance MOhm -capacitance fF -voltage V -current mA
create_clock [get_ports clk]  -period 0.5  -waveform {0 0.25}