Cadence Innovus(TM) Implementation System.
Copyright 2020 Cadence Design Systems, Inc. All rights reserved worldwide.
Version: v20.11-s130_1, built Wed Aug 5 15:53:11 PDT 2020
Options: -cpus 8 -no_gui -files ./scripts/scripts_templates/physical_design.tcl -log ./physical_design/physical_design.log
Date: Sat Jul 19 02:39:57 2025
Host: localhost.localdomain (x86_64 w/Linux 3.10.0-1062.12.1.el7.x86_64) (10cores*10cpus*QEMU Virtual CPU version 2.5+ 16384KB)
OS: CentOS Linux release 7.7.1908 (Core)
License:
invs Innovus Implementation System 20.1 checkout succeeded
8 CPU jobs allowed with the current license(s). Use setMultiCpuUsage to set your required CPU count.
Change the soft stacksize limit to 0.2%RAM (64 mbytes). Set global soft_stack_size_limit to change the value.
setMultiCpuUsage -localCpu 8
**INFO: MMMC transition support version v31-84
<CMD> set_global _enable_mmmc_by_default_flow $CTE::mmmc_default
<CMD> suppressMessage ENCEXT-2799
Sourcing file "./scripts/scripts_templates/physical_design.tcl" ...
<CMD> setMultiCpuUsage -localCpu 8 -cpuAutoAdjust true
<CMD> set defHierChar /
Set Default Input Pin Transition as 0.1 ps.
<CMD> set delaycal_input_transition_delay 0.1ps
<CMD> set fpIsMaxIoHeight 0
<CMD> set init_gnd_net gnd
<CMD> set init_mmmc_file ./scripts/scripts_templates/default.view
<CMD> set init_oa_search_lib {}
<CMD> set init_pwr_net vdd
<CMD> set init_verilog ./physical_design/designs/dlx-structural-strictopt.v
<CMD> set init_lef_file /eda/dk/nangate45/lef/NangateOpenCellLibrary.lef
<CMD> init_design
#% Begin Load MMMC data ... (date=07/19 02:40:38, mem=546.8M)
#% End Load MMMC data ... (date=07/19 02:40:38, total cpu=0:00:00.0, real=0:00:00.0, peak res=547.0M, current mem=547.0M)
high standard low
Loading LEF file /eda/dk/nangate45/lef/NangateOpenCellLibrary.lef ...
Set DBUPerIGU to M2 pitch 380.
viaInitial starts at Sat Jul 19 02:40:38 2025
viaInitial ends at Sat Jul 19 02:40:38 2025
## Check design process and node:
## Both design process and tech node are not set.
Loading view definition file from ./scripts/scripts_templates/default.view
Starting library reading in 'Multi-threaded flow' (with '8' threads)
Reading libsTYP timing library /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib.
**ERROR: (TECHLIB-1346): The attribute 'index_1' defined in group 'ecsm_waveform' on line 393863 is not monotonically increasing for values '0.000041' to '0.000037'. This may lead to undesirable analysis results. The attribute will be ignored. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib)
**ERROR: (TECHLIB-1256): The ecsm_waveform group 1 is being ignored due to errors in this group. This group will be excluded for any further library checks. Refer to the previous messages issued for ecsm_waveform group 1 to find the details of the issues in this group. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib, Line 393862)
**ERROR: (TECHLIB-420): Number of ecsm_waveforms in the 'rise_transition' table on pin ZN of cell OAI222_X2 does not match the number of transition table axis points specified in the template 'Timing_7_7'. Ignoring waveform data. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib, Line 393848)
**ERROR: (TECHLIB-1346): The attribute 'index_1' defined in group 'ecsm_waveform' on line 395723 is not monotonically increasing for values '0.000041' to '0.000037'. This may lead to undesirable analysis results. The attribute will be ignored. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib)
**ERROR: (TECHLIB-1256): The ecsm_waveform group 1 is being ignored due to errors in this group. This group will be excluded for any further library checks. Refer to the previous messages issued for ecsm_waveform group 1 to find the details of the issues in this group. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib, Line 395722)
**ERROR: (TECHLIB-420): Number of ecsm_waveforms in the 'rise_transition' table on pin ZN of cell OAI222_X2 does not match the number of transition table axis points specified in the template 'Timing_7_7'. Ignoring waveform data. (File /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib, Line 395708)
Read 134 cells in library NangateOpenCellLibrary.
Library reading multithread flow ended.
*** End library_loading (cpu=0.10min, real=0.02min, mem=55.0M, fe_cpu=0.69min, fe_real=0.70min, fe_mem=705.6M) ***
#% Begin Load netlist data ... (date=07/19 02:40:39, mem=569.0M)
*** Begin netlist parsing (mem=705.6M) ***
Created 134 new cells from 1 timing libraries.
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist './physical_design/designs/dlx-structural-strictopt.v'
*** Memory Usage v#2 (Current mem = 705.609M, initial mem = 272.285M) ***
*** End netlist parsing (cpu=0:00:00.2, real=0:00:00.0, mem=705.6M) ***
#% End Load netlist data ... (date=07/19 02:40:39, total cpu=0:00:00.2, real=0:00:00.0, peak res=577.0M, current mem=577.0M)
Top level cell is DLX.
Hooked 134 DB cells to tlib cells.
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell DLX ...
*** Netlist is unique.
** info: there are 183 modules.
** info: there are 9978 stdCell insts.
*** Memory Usage v#2 (Current mem = 724.523M, initial mem = 272.285M) ***
Generated pitch 1.68 in metal10 is different from 1.6 defined in technology file in preferred direction.
Generated pitch 0.84 in metal8 is different from 0.8 defined in technology file in preferred direction.
Generated pitch 0.84 in metal7 is different from 0.8 defined in technology file in preferred direction.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Default Input Pin Transition as 0.1 ps.
Extraction setup Started
Initializing multi-corner RC extraction with 1 active RC Corners ...
Reading Capacitance Table File /eda/dk/nangate45/lef/captables/NCSU_FreePDK_45nm.capTbl ...
Cap table was created using Encounter 08.10-p004_1.
Process name: master_techFreePDK45.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :
Analysis View: default
RC-Corner Name : standard
RC-Corner Index : 0
RC-Corner Temperature : 300 Celsius
RC-Corner Cap Table : '/eda/dk/nangate45/lef/captables/NCSU_FreePDK_45nm.capTbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1 {1 1 1}
RC-Corner PostRoute Cap Factor : 1 {1 1 1}
RC-Corner PostRoute XCap Factor : 1 {1 1 1}
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 {1 1 1} [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 {1 1 1} [Derived from postRoute_res (effortLevel low)]
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*Info: initialize multi-corner CTS.
Reading timing constraints file './physical_design/constraints/dlx-synthesized_constraints-strictopt.sdc' ...
Current (total cpu=0:00:43.3, real=0:00:44.0, peak res=806.4M, current mem=805.7M)
**WARN: (TCLCMD-1461): Skipped unsupported command: set_units (File ./physical_design/constraints/dlx-synthesized_constraints-strictopt.sdc, Line 8).
INFO (CTE): Reading of timing constraints file ./physical_design/constraints/dlx-synthesized_constraints-strictopt.sdc completed, with 1 WARNING
Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak res=813.0M, current mem=813.0M)
Current (total cpu=0:00:43.4, real=0:00:44.0, peak res=813.0M, current mem=813.0M)
Total number of combinational cells: 99
Total number of sequential cells: 29
Total number of tristate cells: 6
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32 CLKBUF_X1 CLKBUF_X2 CLKBUF_X3
Total number of usable buffers: 9
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
Total number of usable inverters: 6
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells:
Total number of identified usable delay cells: 0
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
No delay cells were detected in the set of buffers. Buffers will be used to fix hold violations.
*** Summary of all messages that are not suppressed in this session:
Severity ID Count Summary
WARNING TCLCMD-1461 1 Skipped unsupported command: %s
ERROR TECHLIB-420 2 Number of ecsm_waveforms in the '%s' tab...
ERROR TECHLIB-1256 2 The %s is being ignored due to errors in...
ERROR TECHLIB-1346 2 The attribute '%s' defined in group '%s'...
*** Message Summary: 1 warning(s), 6 error(s)
<CMD> getIoFlowFlag
<CMD> setIoFlowFlag 0
<CMD> floorPlan -coreMarginsBy die -site FreePDK45_38x28_10R_NP_162NW_34O -r 1.0 0.6 5 5 5 5
Generated pitch 1.68 in metal10 is different from 1.6 defined in technology file in preferred direction.
Generated pitch 0.84 in metal8 is different from 0.8 defined in technology file in preferred direction.
Generated pitch 0.84 in metal7 is different from 0.8 defined in technology file in preferred direction.
**WARN: (IMPFP-325): Floorplan of the design is resized. All current floorplan objects are automatically derived based on specified new floorplan. This may change blocks, fixed standard cells, existing routes and blockages.
<CMD> uiSetTool select
<CMD> getIoFlowFlag
<CMD> fit
<CMD> saveDesign ./physical_design/1_stage_init.enc
#% Begin save design ... (date=07/19 02:40:42, mem=844.4M)
% Begin Save ccopt configuration ... (date=07/19 02:40:42, mem=846.4M)
% End Save ccopt configuration ... (date=07/19 02:40:42, total cpu=0:00:00.1, real=0:00:00.0, peak res=847.3M, current mem=847.3M)
% Begin Save netlist data ... (date=07/19 02:40:42, mem=847.3M)
Writing Binary DB to ./physical_design/1_stage_init.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:40:42, total cpu=0:00:00.1, real=0:00:00.0, peak res=875.1M, current mem=848.2M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/1_stage_init.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:40:42, mem=849.5M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:40:42, total cpu=0:00:00.0, real=0:00:00.0, peak res=849.5M, current mem=849.5M)
Saving preference file ./physical_design/1_stage_init.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Saving property file in separate thread ...
Save Adaptive View Pruning View Names to Binary file
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
Saving property file ./physical_design/1_stage_init.enc.dat/DLX.prop
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1034.5M) ***
*** Completed saveRoute (cpu=0:00:00.0 real=0:00:00.0 mem=1034.5M) ***
TAT_INFO: ::saveRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveSymbolTable REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 0 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:40:43, mem=854.7M)
% End Save power constraints data ... (date=07/19 02:40:43, total cpu=0:00:00.0, real=0:00:00.0, peak res=854.8M, current mem=854.8M)
high standard low
Generated self-contained design 1_stage_init.enc.dat
#% End save design ... (date=07/19 02:40:56, total cpu=0:00:13.3, real=0:00:14.0, peak res=887.0M, current mem=860.0M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> setAddRingMode -ring_target default -extend_over_row 0 -ignore_rows 0 -avoid_short 0 -skip_crossing_trunks none -stacked_via_top_layer metal10 -stacked_via_bottom_layer metal1 -via_using_exact_crossover_size 1 -orthogonal_only true -skip_via_on_pin { standardcell } -skip_via_on_wire_shape { noshape }
The ring targets are set to core/block ring wires.
addRing command will consider rows while creating rings.
addRing command will disallow rings to go over rows.
addRing command will ignore shorts while creating rings.
<CMD> addRing -nets {vdd gnd} -type core_rings -follow core -layer {top metal9 bottom metal9 left metal10 right metal10} -width {top 0.8 bottom 0.8 left 0.8 right 0.8} -spacing {top 0.8 bottom 0.8 left 0.8 right 0.8} -offset {top 1.8 bottom 1.8 left 1.8 right 1.8} -center 1 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid None
#% Begin addRing (date=07/19 02:40:56, mem=860.0M)
Loading cell geometries (cpu: 0:00:00.0, real: 0:00:00.0, peak mem: 1017.9M)
Ring generation is complete.
vias are now being generated.
addRing created 8 wires.
ViaGen created 8 vias, deleted 0 via to avoid violation.
+--------+----------------+----------------+
| Layer | Created | Deleted |
+--------+----------------+----------------+
| metal9 | 4 | NA |
| via9 | 8 | 0 |
| metal10| 4 | NA |
+--------+----------------+----------------+
#% End addRing (date=07/19 02:40:56, total cpu=0:00:00.1, real=0:00:00.0, peak res=861.9M, current mem=861.9M)
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> set sprCreateIeRingOffset 1.0
<CMD> set sprCreateIeRingThreshold 1.0
<CMD> set sprCreateIeRingJogDistance 1.0
<CMD> set sprCreateIeRingLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> setAddStripeMode -ignore_block_check false -break_at none -route_over_rows_only false -rows_without_stripes_only false -extend_to_closest_target none -stop_at_last_wire_for_area false -partial_set_thru_domain false -ignore_nondefault_domains false -trim_antenna_back_to_shape none -spacing_type edge_to_edge -spacing_from_block 0 -stripe_min_length stripe_width -stacked_via_top_layer metal10 -stacked_via_bottom_layer metal1 -via_using_exact_crossover_size false -split_vias false -orthogonal_only true -allow_jog { padcore_ring block_ring } -skip_via_on_pin { standardcell } -skip_via_on_wire_shape { noshape }
addStripe will allow jog to connect padcore ring and block ring.
Stripes will stop at the boundary of the specified area.
When breaking rings, the power planner will consider the existence of blocks.
Stripes will not extend to closest target.
The power planner will set stripe antenna targets to none (no trimming allowed).
Stripes will not be created over regions without power planning wires.
The entire stripe set will break at the domain if one of the nets is not in the domain.
addStripe will break automatically at non-default domains when generating global stripes over the core area or default domain.
Offset for stripe breaking is set to 0.
<CMD> addStripe -nets {vdd gnd} -layer metal10 -direction vertical -width 0.8 -spacing 0.8 -set_to_set_distance 20 -start_from left -start_offset 15 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit metal10 -padcore_ring_bottom_layer_limit metal1 -block_ring_top_layer_limit metal10 -block_ring_bottom_layer_limit metal1 -use_wire_group 0 -snap_wire_center_to_grid None
#% Begin addStripe (date=07/19 02:40:56, mem=861.9M)
Initialize fgc environment(mem: 1017.9M) ... fail and won't use fgc to check drc(cpu: 0:00:00.0, real: 0:00:00.0, peak mem: 1017.9M)
Loading cell geometries (cpu: 0:00:00.0, real: 0:00:00.0, peak mem: 1017.9M)
Loading wires (cpu: 0:00:00.0, real: 0:00:00.0, peak mem: 1017.9M)
Loading via instances (cpu: 0:00:00.0, real: 0:00:00.0, peak mem: 1017.9M)
Starting stripe generation ...
Non-Default Mode Option Settings :
NONE
**WARN: (IMPPP-4055): The run time of addStripe will degrade with multiple cpu setting according to the number of stripe sets, ignore the setting of setMultiCpuUsage in addStripe.
Type 'man IMPPP-4055' for more detail.
Stripe generation is complete.
vias are now being generated.
addStripe created 18 wires.
ViaGen created 36 vias, deleted 0 via to avoid violation.
+--------+----------------+----------------+
| Layer | Created | Deleted |
+--------+----------------+----------------+
| via9 | 36 | 0 |
| metal10| 18 | NA |
+--------+----------------+----------------+
#% End addStripe (date=07/19 02:40:56, total cpu=0:00:00.1, real=0:00:00.0, peak res=863.0M, current mem=863.0M)
<CMD> saveDesign ./physical_design/2_stage_route_placement.enc
#% Begin save design ... (date=07/19 02:40:56, mem=863.0M)
% Begin Save ccopt configuration ... (date=07/19 02:40:56, mem=863.0M)
% End Save ccopt configuration ... (date=07/19 02:40:56, total cpu=0:00:00.0, real=0:00:00.0, peak res=863.0M, current mem=863.0M)
% Begin Save netlist data ... (date=07/19 02:40:56, mem=863.0M)
Writing Binary DB to ./physical_design/2_stage_route_placement.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:40:56, total cpu=0:00:00.1, real=0:00:00.0, peak res=863.7M, current mem=863.7M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/2_stage_route_placement.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:40:56, mem=863.9M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:40:56, total cpu=0:00:00.0, real=0:00:00.0, peak res=863.9M, current mem=863.9M)
Saving preference file ./physical_design/2_stage_route_placement.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
Save Adaptive View Pruning View Names to Binary file
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
Saving property file ./physical_design/2_stage_route_placement.enc.dat/DLX.prop
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1075.5M) ***
*** Completed saveRoute (cpu=0:00:00.1 real=0:00:00.0 mem=1075.5M) ***
TAT_INFO: ::saveRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveSymbolTable REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 1 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:40:58, mem=864.7M)
% End Save power constraints data ... (date=07/19 02:40:58, total cpu=0:00:00.0, real=0:00:00.0, peak res=864.7M, current mem=864.7M)
high standard low
Generated self-contained design 2_stage_route_placement.enc.dat
#% End save design ... (date=07/19 02:41:10, total cpu=0:00:13.0, real=0:00:14.0, peak res=898.2M, current mem=865.2M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> setSrouteMode -viaConnectToShape { noshape }
<CMD> sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { metal1(1) metal10(10) } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } -allowJogging 1 -crossoverViaLayerRange { metal1(1) metal10(10) } -nets { vdd gnd } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { metal1(1) metal10(10) }
#% Begin sroute (date=07/19 02:41:10, mem=865.2M)
*** Begin SPECIAL ROUTE on Sat Jul 19 02:41:11 2025 ***
SPECIAL ROUTE ran on directory: /home/ms25.2/Microlectronics-Systems-Lab/DLX_Pro
SPECIAL ROUTE ran on machine: localhost.localdomain (Linux 3.10.0-1062.12.1.el7.x86_64 x86_64 2.00Ghz)
Begin option processing ...
srouteConnectPowerBump set to false
routeSelectNet set to "vdd gnd"
routeSpecial set to true
srouteBlockPin set to "useLef"
srouteBottomLayerLimit set to 1
srouteBottomTargetLayerLimit set to 1
srouteConnectConverterPin set to false
srouteCrossoverViaBottomLayer set to 1
srouteCrossoverViaTopLayer set to 10
srouteFloatingStripeTarget set to "blockring padring ring stripe ringpin blockpin followpin"
srouteFollowCorePinEnd set to 3
srouteJogControl set to "preferWithChanges differentLayer"
srouteNoViaOnWireShape set to "padring ring stripe blockring blockpin coverpin blockwire corewire followpin iowire"
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
srouteStopBlockPin set to "nearestTarget"
srouteTopLayerLimit set to 10
srouteTopTargetLayerLimit set to 10
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 2206.00 megs.
Reading DB technology information...
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
Read in 20 layers, 10 routing layers, 1 overlap layer
Read in 134 macros, 37 used
Read in 37 components
37 core components: 37 unplaced, 0 placed, 0 fixed
Read in 2 logical pins
Read in 2 nets
Read in 2 special nets, 2 routed
2 nets selected.
Begin power routing ...
**WARN: (IMPSR-1253): Unable to find any standard cell pin connected to the vdd net.
Run the globalNetConnect command or change the CPF file to ensure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as 'USE POWER' or 'USE GROUND' for the connection.
**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of the vdd net were not found in the design. Check netlist or change the parameter value to include block pins in the design.
**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the vdd net due to unavailability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.
Type 'man IMPSR-1256' for more detail.
Cannot find any AREAIO class pad pin of net vdd. Check net list, or change port class in the technology file, or change option to include pin in given range.
**WARN: (IMPSR-1253): Unable to find any standard cell pin connected to the gnd net.
Run the globalNetConnect command or change the CPF file to ensure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as 'USE POWER' or 'USE GROUND' for the connection.
**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of the gnd net were not found in the design. Check netlist or change the parameter value to include block pins in the design.
**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the gnd net due to unavailability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.
Type 'man IMPSR-1256' for more detail.
Cannot find any AREAIO class pad pin of net gnd. Check net list, or change port class in the technology file, or change option to include pin in given range.
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net vdd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net vdd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net gnd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net gnd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net vdd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net vdd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
CPU time for FollowPin 0 seconds
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net gnd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
**WARN: (IMPSR-468): Cannot find any standard cell pin connected to net gnd.
Use setSrouteMode -corePinReferenceMacro <standard cell> to specify a reference macro for followpin connection, or run globalNetConnect command or change CPF file to make sure that the netlist reflects the correct power ground connections. The standard cell pins must be defined as "USE POWER" or "USE GROUND".
CPU time for FollowPin 0 seconds
Number of IO ports routed: 0
Number of Block ports routed: 0
Number of Stripe ports routed: 0
Number of Core ports routed: 270
Number of Pad ports routed: 0
Number of Power Bump ports routed: 0
Number of Followpin connections: 135
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 2262.00 megs.
Begin updating DB with routing results ...
Updating DB with 0 via definition ...Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
sroute created 405 wires.
ViaGen created 2430 vias, deleted 0 via to avoid violation.
+--------+----------------+----------------+
| Layer | Created | Deleted |
+--------+----------------+----------------+
| metal1 | 405 | NA |
| via1 | 270 | 0 |
| via2 | 270 | 0 |
| via3 | 270 | 0 |
| via4 | 270 | 0 |
| via5 | 270 | 0 |
| via6 | 270 | 0 |
| via7 | 270 | 0 |
| via8 | 270 | 0 |
| via9 | 270 | 0 |
+--------+----------------+----------------+
#% End sroute (date=07/19 02:41:11, total cpu=0:00:00.7, real=0:00:01.0, peak res=888.3M, current mem=888.3M)
<CMD> setPlaceMode -prerouteAsObs {1 2 3 4 5 6 7 8}
<CMD> setRouteMode -earlyGlobalHonorMsvRouteConstraint false -earlyGlobalRoutePartitionPinGuide true
<CMD> setEndCapMode -reset
<CMD> setEndCapMode -boundary_tap false
<CMD> setNanoRouteMode -quiet -droutePostRouteSpreadWire 1
<CMD> setNanoRouteMode -quiet -timingEngine {}
<CMD> setUsefulSkewMode -maxSkew false -noBoundary false -useCells {CLKBUF_X3 CLKBUF_X2 CLKBUF_X1 BUF_X32 BUF_X16 BUF_X8 BUF_X4 BUF_X2 BUF_X1 INV_X32 INV_X16 INV_X8 INV_X4 INV_X2 INV_X1} -maxAllowedDelay 1
<CMD> setPlaceMode -reset
-place_detail_preroute_as_obs ""
<CMD> setPlaceMode -congEffort auto -timingDriven 1 -clkGateAware 1 -powerDriven 0 -ignoreScan 1 -reorderScan 1 -ignoreSpare 0 -placeIOPins 1 -moduleAwareSpare 0 -maxRouteLayer 6 -preserveRouting 1 -rmAffectedRouting 0 -checkRoute 0 -swapEEQ 0
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
<CMD> setPlaceMode -fp false
<CMD> place_design
**WARN: (IMPSP-9525): setPlaceMode -maxRouteLayer will overwrite setTrialRouteMode -maxRouteLayer inside placeDesign.
**WARN: (IMPPSP-1003): Found use of 'setRouteMode -earlyGlobalMaxRouteLayer'. This will continue to work in this release; however, it is recommended to use 'setDesignMode -topRoutingLayer' instead.
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
*** Starting placeDesign default flow ***
*** Start deleteBufferTree ***
Multithreaded Timing Analysis is initialized with 8 threads
Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
AAE DB initialization (MEM=1127.82 CPU=0:00:00.0 REAL=0:00:00.0)
siFlow : Timing analysis mode is single, using late cdB files
*summary: 1469 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:00:03.2) ***
**INFO: Enable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 101.
**WARN: (IMPDC-1629): The default delay limit was set to 101. This is less than the default of 1000 and may result in inaccurate delay calculation for nets with a fanout higher than the setting. If needed, the default delay limit may be adjusted by running the command 'set delaycal_use_default_delay_limit'.
Set Default Net Delay as 0 ps.
Set Default Net Load as 0 pF.
**INFO: Analyzing IO path groups for slack adjustment
Effort level <high> specified for reg2reg_tmp.10677 path_group
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1161.98)
Total number of fetched objects 9909
End delay calculation. (MEM=1659.21 CPU=0:00:06.9 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=1509.36 CPU=0:00:08.8 REAL=0:00:03.0)
**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
**INFO: Pre-place timing setting for timing analysis already disabled
Deleted 0 physical inst (cell - / prefix -).
INFO: #ExclusiveGroups=0
INFO: There are no Exclusive Groups.
*** Starting "NanoPlace(TM) placement v#15 (mem=1499.8M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:00.8 mem=1563.9M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:01.0 mem=1563.9M) ***
No user-set net weight.
Net fanout histogram:
2 : 6664 (75.2%) nets
3 : 1586 (17.9%) nets
4 - 14 : 313 (3.5%) nets
15 - 39 : 262 (3.0%) nets
40 - 79 : 37 (0.4%) nets
80 - 159 : 1 (0.0%) nets
160 - 319 : 1 (0.0%) nets
320 - 639 : 0 (0.0%) nets
640 - 1279 : 1 (0.0%) nets
1280 - 2559 : 1 (0.0%) nets
2560 - 5119 : 0 (0.0%) nets
5120+ : 0 (0.0%) nets
Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=auto gpeffort=medium
**WARN: (IMPSP-9042): Scan chains were not defined, -place_global_ignore_scan option will be ignored.
Define the scan chains before using this option.
Type 'man IMPSP-9042' for more detail.
#std cell=8519 (0 fixed + 8519 movable) #buf cell=0 #inv cell=889 #block=0 (0 floating + 0 preplaced)
#ioInst=0 #net=8866 #term=33410 #term/net=3.77, #fixedIo=0, #floatIo=0, #fixedPin=0, #floatPin=2
stdCell: 8519 single + 0 double + 0 multi
Total standard cell length = 14.3832 (mm), area = 0.0201 (mm^2)
Estimated cell power/ground rail width = 0.197 um
Average module density = 0.568.
Density for the design = 0.568.
= stdcell_area 75701 sites (20136 um^2) / alloc_area 133330 sites (35466 um^2).
Pin Density = 0.2506.
= total # of pins 33410 / total area 133330.
Enabling multi-CPU acceleration with 8 CPU(s) for placement
=== lastAutoLevel = 8
Clock gating cells determined by native netlist tracing.
Iteration 1: Total net bbox = 2.614e-09 (1.91e-09 7.01e-10)
Est. stn bbox = 2.732e-09 (2.00e-09 7.36e-10)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 1400.4M
Iteration 2: Total net bbox = 2.614e-09 (1.91e-09 7.01e-10)
Est. stn bbox = 2.732e-09 (2.00e-09 7.36e-10)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1400.4M
Iteration 3: Total net bbox = 1.890e+02 (9.91e+01 8.99e+01)
Est. stn bbox = 2.670e+02 (1.41e+02 1.26e+02)
cpu = 0:00:01.7 real = 0:00:01.0 mem = 1640.3M
Active setup views:
default
Iteration 4: Total net bbox = 5.781e+04 (2.10e+04 3.68e+04)
Est. stn bbox = 7.711e+04 (2.67e+04 5.05e+04)
cpu = 0:00:16.0 real = 0:00:04.0 mem = 1640.3M
Iteration 5: Total net bbox = 7.521e+04 (3.41e+04 4.11e+04)
Est. stn bbox = 1.057e+05 (4.73e+04 5.84e+04)
cpu = 0:00:17.4 real = 0:00:04.0 mem = 1640.3M
Iteration 6: Total net bbox = 8.452e+04 (3.85e+04 4.60e+04)
Est. stn bbox = 1.231e+05 (5.63e+04 6.68e+04)
cpu = 0:00:28.8 real = 0:00:06.0 mem = 1769.4M
Iteration 7: Total net bbox = 8.759e+04 (4.10e+04 4.66e+04)
Est. stn bbox = 1.262e+05 (5.89e+04 6.73e+04)
cpu = 0:00:00.8 real = 0:00:01.0 mem = 1545.3M
Iteration 8: Total net bbox = 8.759e+04 (4.10e+04 4.66e+04)
Est. stn bbox = 1.262e+05 (5.89e+04 6.73e+04)
cpu = 0:00:16.3 real = 0:00:09.0 mem = 1651.7M
Iteration 9: Total net bbox = 9.243e+04 (4.36e+04 4.88e+04)
Est. stn bbox = 1.329e+05 (6.24e+04 7.05e+04)
cpu = 0:00:25.7 real = 0:00:06.0 mem = 1708.2M
Iteration 10: Total net bbox = 9.243e+04 (4.36e+04 4.88e+04)
Est. stn bbox = 1.329e+05 (6.24e+04 7.05e+04)
cpu = 0:00:17.0 real = 0:00:10.0 mem = 1676.2M
Iteration 11: Total net bbox = 1.010e+05 (4.70e+04 5.40e+04)
Est. stn bbox = 1.409e+05 (6.58e+04 7.51e+04)
cpu = 0:00:50.6 real = 0:00:11.0 mem = 1710.2M
Iteration 12: Total net bbox = 1.010e+05 (4.70e+04 5.40e+04)
Est. stn bbox = 1.409e+05 (6.58e+04 7.51e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1710.2M
Iteration 13: Total net bbox = 1.010e+05 (4.70e+04 5.40e+04)
Est. stn bbox = 1.409e+05 (6.58e+04 7.51e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1710.2M
*** cost = 1.010e+05 (4.70e+04 5.40e+04) (cpu for global=0:02:55) real=0:00:53.0***
Placement multithread real runtime: 0:00:53.0 with 8 threads.
Info: 0 clock gating cells identified, 0 (on average) moved 0/5
Solver runtime cpu: 0:02:17 real: 0:00:31.2
Core Placement runtime cpu: 0:02:21 real: 0:00:33.0
**WARN: (IMPSP-9025): No scan chain specified/traced.
Type 'man IMPSP-9025' for more detail.
*** Starting refinePlace (0:04:29 mem=1710.2M) ***
Total net bbox length = 1.010e+05 (4.705e+04 5.397e+04) (ext = 1.152e+01)
Move report: Detail placement moves 8519 insts, mean move: 0.95 um, max move: 11.84 um
Max move on inst (datapath_inst/execute_inst/U447): (136.00, 176.05) --> (139.65, 184.24)
Runtime: CPU: 0:00:05.3 REAL: 0:00:03.0 MEM: 1710.2MB
Summary Report:
Instances move: 8519 (out of 8519 movable)
Instances flipped: 0
Mean displacement: 0.95 um
Max displacement: 11.84 um (Instance: datapath_inst/execute_inst/U447) (135.998, 176.052) -> (139.65, 184.24)
Length: 5 sites, height: 1 rows, site name: FreePDK45_38x28_10R_NP_162NW_34O, cell type: OR3_X1
Total net bbox length = 9.732e+04 (4.320e+04 5.412e+04) (ext = 1.209e+01)
Runtime: CPU: 0:00:05.4 REAL: 0:00:03.0 MEM: 1710.2MB
*** Finished refinePlace (0:04:34 mem=1710.2M) ***
*** End of Placement (cpu=0:03:06, real=0:00:59.0, mem=1710.2M) ***
default core: bins with density > 0.750 = 0.00 % ( 0 / 196 )
Density distribution unevenness ratio = 8.425%
*** Free Virtual Timing Model ...(mem=1710.2M)
Starting IO pin assignment...
The design is not routed. Using placement based method for pin assignment.
Completed IO pin assignment.
**INFO: Enable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 101.
**WARN: (IMPDC-1629): The default delay limit was set to 101. This is less than the default of 1000 and may result in inaccurate delay calculation for nets with a fanout higher than the setting. If needed, the default delay limit may be adjusted by running the command 'set delaycal_use_default_delay_limit'.
Set Default Net Delay as 0 ps.
Set Default Net Load as 0 pF.
**INFO: Analyzing IO path groups for slack adjustment
Effort level <high> specified for reg2reg_tmp.10677 path_group
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1698.7)
Total number of fetched objects 9909
End delay calculation. (MEM=1953.29 CPU=0:00:06.6 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=1953.29 CPU=0:00:07.8 REAL=0:00:02.0)
**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Info: Disable timing driven in postCTS congRepair.
Starting congRepair ...
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] Read 2700 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 2700
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=8866 numIgnoredNets=0
[NR-eGR] There are 1 clock nets ( 0 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 8866
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8866 net(s) in layer range [2, 6]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 1.355606e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (1) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 3( 0.02%) ( 0.02%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 3( 0.02%) ( 0.02%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 6( 0.01%) ( 0.01%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
Early Global Route congestion estimation runtime: 0.62 seconds, mem = 1631.8M
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row bins)
Skipped repairing congestion.
[NR-eGR] Started Export DB wires ( Curr Mem: 1631.79 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 1631.79 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.18 sec, Real: 0.03 sec, Curr Mem: 1631.79 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 1631.79 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.03 sec, Real: 0.01 sec, Curr Mem: 1631.79 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.22 sec, Real: 0.05 sec, Curr Mem: 1631.79 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33408
[NR-eGR] metal2 (2V) length: 3.581426e+04um, number of vias: 43388
[NR-eGR] metal3 (3H) length: 5.944599e+04um, number of vias: 16168
[NR-eGR] metal4 (4V) length: 2.719805e+04um, number of vias: 1458
[NR-eGR] metal5 (5H) length: 6.166190e+03um, number of vias: 1293
[NR-eGR] metal6 (6V) length: 1.418720e+04um, number of vias: 0
[NR-eGR] Total length: 1.428117e+05um, number of vias: 95715
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 4.462400e+03um
[NR-eGR] --------------------------------------------------------------------------
Early Global Route wiring runtime: 0.21 seconds, mem = 1631.8M
Tdgp not successfully inited but do clear! skip clearing
End of congRepair (cpu=0:00:02.3, real=0:00:01.0)
*** Finishing placeDesign default flow ***
**placeDesign ... cpu = 0: 3:38, real = 0: 1:16, mem = 1629.8M **
Tdgp not successfully inited but do clear! skip clearing
**WARN: (IMPPSP-1003): Found use of 'setRouteMode -earlyGlobalMaxRouteLayer'. This will continue to work in this release; however, it is recommended to use 'setDesignMode -topRoutingLayer' instead.
**WARN: (IMPSP-9526): Restoring setTrialRouteMode -maxRouteLayer after placeDesign. Use 'setTrialRouteMode -maxRoutingLayer N' to set maximum routing layer.
*** Summary of all messages that are not suppressed in this session:
Severity ID Count Summary
WARNING IMPDC-1629 2 The default delay limit was set to %d. T...
WARNING IMPSP-9525 1 setPlaceMode -maxRouteLayer will overwri...
WARNING IMPSP-9526 1 Restoring setTrialRouteMode -maxRouteLay...
WARNING IMPSP-9025 1 No scan chain specified/traced.
WARNING IMPSP-9042 1 Scan chains were not defined, -place_glo...
WARNING IMPPSP-1003 2 Found use of '%s'. This will continue to...
*** Message Summary: 8 warning(s), 0 error(s)
<CMD> saveDesign ./physical_design/3_stage_preCTS.enc
#% Begin save design ... (date=07/19 02:42:27, mem=1102.5M)
% Begin Save ccopt configuration ... (date=07/19 02:42:27, mem=1102.5M)
% End Save ccopt configuration ... (date=07/19 02:42:27, total cpu=0:00:00.0, real=0:00:00.0, peak res=1102.6M, current mem=1102.6M)
% Begin Save netlist data ... (date=07/19 02:42:27, mem=1102.6M)
Writing Binary DB to ./physical_design/3_stage_preCTS.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:42:28, total cpu=0:00:00.2, real=0:00:01.0, peak res=1102.6M, current mem=1102.5M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/3_stage_preCTS.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:42:28, mem=1102.7M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:42:28, total cpu=0:00:00.0, real=0:00:00.0, peak res=1102.7M, current mem=1102.7M)
Saving preference file ./physical_design/3_stage_preCTS.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Saving property file ./physical_design/3_stage_preCTS.enc.dat/DLX.prop
Save Adaptive View Pruning View Names to Binary file
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=1684.3M) ***
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveRoute (cpu=0:00:00.2 real=0:00:01.0 mem=1684.3M) ***
TAT_INFO: ::saveRoute REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveSymbolTable REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 0 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:42:29, mem=1103.1M)
% End Save power constraints data ... (date=07/19 02:42:29, total cpu=0:00:00.0, real=0:00:00.0, peak res=1103.1M, current mem=1103.1M)
high standard low
Generated self-contained design 3_stage_preCTS.enc.dat
#% End save design ... (date=07/19 02:42:41, total cpu=0:00:12.8, real=0:00:14.0, peak res=1103.1M, current mem=1102.2M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> setDelayCalMode -siAware false
<CMD> timeDesign -preCTS -pathReports -drvReports -slackReports -numPaths 10 -prefix DLX_preCTS_setup -outDir ./physical_design/timingReport
Setting timing_disable_library_data_to_data_checks to 'true'.
Setting timing_disable_user_data_to_data_checks to 'true'.
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1625.3M)
Extraction called for design 'DLX' of instances=8519 and nets=9234 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.3 Real Time: 0:00:00.0 MEM: 1625.332M)
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1715.25)
Total number of fetched objects 9909
End delay calculation. (MEM=2036.16 CPU=0:00:07.6 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2036.16 CPU=0:00:09.0 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:11.3 real=0:00:02.0 totSessionCpu=0:05:17 mem=2036.2M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.337 | 0.652 | 0.337 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 281 (281) | -2.549 | 281 (281) |
| max_tran | 31 (1434) | -0.779 | 31 (1434) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.777%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 15.99 sec
Total Real time: 7.0 sec
Total Memory Usage: 1742.691406 Mbytes
<CMD> timeDesign -preCTS -hold -pathReports -slackReports -numPaths 10 -prefix DLX_preCTS_hold -outDir ./physical_design/timingReport
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1656.2M)
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1725.47)
Total number of fetched objects 9909
End delay calculation. (MEM=2045.26 CPU=0:00:08.1 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2045.26 CPU=0:00:09.6 REAL=0:00:02.0)
Turning on fast DC mode./n*** Done Building Timing Graph (cpu=0:00:11.5 real=0:00:02.0 totSessionCpu=0:05:33 mem=2045.3M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Hold views included:
default
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.341 | 0.075 | -0.341 |
| TNS (ns):|-245.034 | 0.000 |-245.034 |
| Violating Paths:| 1308 | 0 | 1308 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
Density: 56.777%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 15.09 sec
Total Real time: 4.0 sec
Total Memory Usage: 1654.742188 Mbytes
<CMD> report_timing > ./physical_design/report_timing_preCTS.txt
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1729.14)
Total number of fetched objects 9909
End delay calculation. (MEM=2076.94 CPU=0:00:07.0 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2076.94 CPU=0:00:08.2 REAL=0:00:01.0)
<CMD> create_ccopt_clock_tree_spec
Creating clock tree spec for modes (timing configs): coherent-synthesis
extract_clock_generator_skew_groups=true: create_ccopt_clock_tree_spec will generate skew groups with a name prefix of "_clock_gen" to balance clock generator connected flops with the clock generator they drive.
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Ignoring AAE DB Resetting ...
Analyzing clock structure...
Analyzing clock structure done.
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Extracting original clock gating for clk...
clock_tree clk contains 1325 sinks and 0 clock gates.
Extraction for clk complete.
Extracting original clock gating for clk done.
The skew group clk/coherent-synthesis was created. It contains 1325 sinks and 1 sources.
Checking clock tree convergence...
Checking clock tree convergence done.
<CMD> set_ccopt_property target_max_trans 0.05
<CMD> set_ccopt_property target_skew 0.02
<CMD> ccopt_design
#% Begin ccopt_design (date=07/19 02:42:56, mem=1162.0M)
Turning off fast DC mode./nRuntime...
**INFO: User's settings:
setNanoRouteMode -droutePostRouteSpreadWire 1
setNanoRouteMode -extractThirdPartyCompatible false
setNanoRouteMode -timingEngine {}
setExtractRCMode -engine preRoute
setDelayCalMode -enable_high_fanout true
setDelayCalMode -eng_copyNetPropToNewNet true
setDelayCalMode -engine aae
setDelayCalMode -ignoreNetLoad false
setDelayCalMode -SIAware false
setOptMode -preserveAllSequential true
setPlaceMode -maxRouteLayer 6
setPlaceMode -place_design_floorplan_mode false
setPlaceMode -place_detail_check_route false
setPlaceMode -place_detail_preserve_routing true
setPlaceMode -place_detail_remove_affected_routing false
setPlaceMode -place_detail_swap_eeq_cells false
setPlaceMode -place_global_clock_gate_aware true
setPlaceMode -place_global_cong_effort auto
setPlaceMode -place_global_ignore_scan true
setPlaceMode -place_global_ignore_spare false
setPlaceMode -place_global_module_aware_spare false
setPlaceMode -place_global_place_io_pins true
setPlaceMode -place_global_reorder_scan true
setPlaceMode -powerDriven false
setPlaceMode -timingDriven true
setRouteMode -earlyGlobalHonorMsvRouteConstraint false
setRouteMode -earlyGlobalRoutePartitionPinGuide true
(ccopt_design): CTS Engine: auto. Used Spec: pre-existing CCOPT spec.
Placement constraints of type 'region' or 'fence' will not be downgraded to 'guide' because the property change_fences_to_guides has been set to false.
Set place::cacheFPlanSiteMark to 1
'setDesignMode -flowEffort standard' => 'setOptMode -usefulSkewCCOpt standard'
Using CCOpt effort standard.
CCOpt::Phase::Initialization...
Check Prerequisites...
Leaving CCOpt scope - CheckPlace...
Begin checking placement ... (start mem=1667.4M, init mem=1699.4M)
*info: Placed = 8519
*info: Unplaced = 0
Placement Density:56.78%(20136/35466)
Placement Density (including fixed std cells):56.78%(20136/35466)
Finished checkPlace (total: cpu=0:00:00.3, real=0:00:00.0; vio checks: cpu=0:00:00.3, real=0:00:00.0; mem=1699.4M)
Leaving CCOpt scope - CheckPlace done. (took cpu=0:00:00.4 real=0:00:00.2)
Innovus will update I/O latencies
Found 0 ideal nets, 0 pins with transition annotations, 0 instances with delay annotations, 0 nets with delay annotations, refer to logv for details.
Check Prerequisites done. (took cpu=0:00:00.4 real=0:00:00.2)
CCOpt::Phase::Initialization done. (took cpu=0:00:00.4 real=0:00:00.2)
Executing ccopt post-processing.
Synthesizing clock trees with CCOpt...
CCOpt::Phase::PreparingToBalance...
Leaving CCOpt scope - Initializing power interface...
Leaving CCOpt scope - Initializing power interface done. (took cpu=0:00:00.0 real=0:00:00.0)
Found 0 advancing pin insertion delay (0.000% of 1325 clock tree sinks)
Found 0 delaying pin insertion delay (0.000% of 1325 clock tree sinks)
Leaving CCOpt scope - optDesignGlobalRouteStep...
[NR-eGR] Started Early Global Route kernel ( Curr Mem: 1699.43 MB )
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 4704 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 4704
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=8866 numIgnoredNets=0
[NR-eGR] There are 1 clock nets ( 0 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 8866
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8866 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 1.355606e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (1) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 2( 0.01%) ( 0.01%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 2( 0.01%) ( 0.01%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 4( 0.00%) ( 0.00%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 1705.52 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 1705.52 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.18 sec, Real: 0.03 sec, Curr Mem: 1705.53 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 1705.53 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.05 sec, Real: 0.02 sec, Curr Mem: 1705.53 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.25 sec, Real: 0.06 sec, Curr Mem: 1705.53 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33408
[NR-eGR] metal2 (2V) length: 3.578450e+04um, number of vias: 43386
[NR-eGR] metal3 (3H) length: 5.945076e+04um, number of vias: 16174
[NR-eGR] metal4 (4V) length: 2.714298e+04um, number of vias: 1426
[NR-eGR] metal5 (5H) length: 6.015270e+03um, number of vias: 1261
[NR-eGR] metal6 (6V) length: 1.385817e+04um, number of vias: 30
[NR-eGR] metal7 (7H) length: 1.379900e+02um, number of vias: 18
[NR-eGR] metal8 (8V) length: 4.267200e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.428164e+05um, number of vias: 95703
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 4.463630e+03um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 2.27 sec, Real: 0.84 sec, Curr Mem: 1701.53 MB )
Leaving CCOpt scope - optDesignGlobalRouteStep done. (took cpu=0:00:02.3 real=0:00:00.9)
Rebuilding timing graph...
Rebuilding timing graph done.
Legalization setup...
Using cell based legalization.
Initializing placement interface...
Use check_library -place or consult logv if problems occur.
Initializing placement interface done.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Legalization setup done. (took cpu=0:00:00.3 real=0:00:00.2)
Validating CTS configuration...
Checking module port directions...
Checking module port directions done. (took cpu=0:00:00.0 real=0:00:00.0)
Non-default CCOpt properties:
cts_merge_clock_gates is set for at least one object
cts_merge_clock_logic is set for at least one object
route_type is set for at least one object
target_max_trans is set for at least one object
target_skew is set for at least one object
Route type trimming info:
No route type modifications were made.
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
**WARN: (IMPCCOPT-1184): The library has no usable balanced inverters for power domain auto-default, while balancing clock_tree clk. If this is not intended behavior, you can specify a list of lib_cells to use with the inverter_cells property.
Clock tree balancer configuration for clock_tree clk:
Non-default CCOpt properties:
cts_merge_clock_gates: true (default: false)
cts_merge_clock_logic: true (default: false)
route_type (leaf): default_route_type_leaf (default: default)
route_type (trunk): default_route_type_nonleaf (default: default)
route_type (top): default_route_type_nonleaf (default: default)
For power domain auto-default:
Buffers: CLKBUF_X3 CLKBUF_X2 CLKBUF_X1
Inverters:
Clock gates (with test): CLKGATETST_X8 CLKGATETST_X4 CLKGATETST_X2 CLKGATETST_X1
Clock gates (no test): CLKGATE_X8 CLKGATE_X4 CLKGATE_X2 CLKGATE_X1
Unblocked area available for placement of any clock cells in power_domain auto-default: 35465.780um^2
Top Routing info:
Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Mask Constraint: 0; Source: route_type.
Trunk Routing info:
Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: route_type.
Leaf Routing info:
Route-type name: default_route_type_leaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: route_type.
For timing_corner std-typ:both, late and power domain auto-default:
Slew time target (leaf): 0.050ns
Slew time target (trunk): 0.050ns
Slew time target (top): 0.050ns (Note: no nets are considered top nets in this clock tree)
Buffer unit delay: 0.042ns
Buffer max distance: 383.704um
Fastest wire driving cells and distances:
Buffer : {lib_cell:CLKBUF_X3, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=383.704um, saturatedSlew=0.043ns, speed=3996.916um per ns, cellArea=3.466um^2 per 1000um}
Clock gate (with test): {lib_cell:CLKGATETST_X8, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=550.588um, saturatedSlew=0.043ns, speed=5629.734um per ns, cellArea=14.010um^2 per 1000um}
Clock gate (no test): {lib_cell:CLKGATE_X8, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=549.804um, saturatedSlew=0.043ns, speed=5842.763um per ns, cellArea=12.579um^2 per 1000um}
Logic Sizing Table:
----------------------------------------------------------
Cell Instance count Source Eligible library cells
----------------------------------------------------------
(empty table)
----------------------------------------------------------
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Clock tree balancer configuration for skew_group clk/coherent-synthesis:
Sources: pin clk
Total number of sinks: 1325
Delay constrained sinks: 1325
Non-leaf sinks: 0
Ignore pins: 0
Timing corner std-typ:both.late:
Skew target: 0.042ns
**WARN: (IMPCCOPT-1361): Routing configuration for top nets in clock tree clk: preferred layers metal3-metal4 are outside NanoRoute configured layer range. This is likely to cause routing correlation issues.
**WARN: (IMPCCOPT-1361): Routing configuration for trunk nets in clock tree clk: preferred layers metal3-metal4 are outside NanoRoute configured layer range. This is likely to cause routing correlation issues.
**WARN: (IMPCCOPT-1361): Routing configuration for leaf nets in clock tree clk: preferred layers metal3-metal4 are outside NanoRoute configured layer range. This is likely to cause routing correlation issues.
Primary reporting skew groups are:
skew_group clk/coherent-synthesis with 1325 clock sinks
Clock DAG stats initial state:
cell counts : b=0, i=0, icg=0, nicg=0, l=0, total=0
cell areas : b=0.000um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=0.000um^2
hp wire lengths : top=0.000um, trunk=0.000um, leaf=0.000um, total=0.000um
Have 8 CPUs available for CTS. Selected algorithms will run multithreaded.
No ideal or dont_touch nets found in the clock tree
No dont_touch hnets found in the clock tree
Validating CTS configuration done. (took cpu=0:00:01.8 real=0:00:01.8)
CCOpt configuration status: all checks passed.
Adding exclusion drivers to pins that are effective_sink_type exclude...
Adding exclusion drivers (these will be instances of the smallest area library cells).
No exclusion drivers are needed.
Adding exclusion drivers to pins that are effective_sink_type exclude done.
Antenna diode management...
Found 0 antenna diodes in the clock trees.
Antenna diode management done.
Adding driver cells for primary IOs...
----------------------------------------------------------------------------------------------
CCOpt reported the following when adding drivers below input ports and above output ports
----------------------------------------------------------------------------------------------
(empty table)
----------------------------------------------------------------------------------------------
Adding driver cells for primary IOs done.
Adding driver cell for primary IO roots...
Adding driver cell for primary IO roots done.
Maximizing clock DAG abstraction...
Maximizing clock DAG abstraction done.
CCOpt::Phase::PreparingToBalance done. (took cpu=0:00:07.3 real=0:00:03.6)
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Synthesizing clock trees...
Preparing To Balance...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Merging duplicate siblings in DAG...
Clock DAG stats before merging:
cell counts : b=0, i=0, icg=0, nicg=0, l=0, total=0
cell areas : b=0.000um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=0.000um^2
hp wire lengths : top=0.000um, trunk=0.000um, leaf=0.000um, total=0.000um
Resynthesising clock tree into netlist...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Resynthesising clock tree into netlist done.
Disconnecting clock tree from netlist...
Disconnecting clock tree from netlist done.
Merging duplicate siblings in DAG done.
Preparing To Balance done. (took cpu=0:00:00.3 real=0:00:00.2)
CCOpt::Phase::Construction...
Stage::Clustering...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Clustering...
Initialize for clustering...
Clock DAG stats before clustering:
cell counts : b=0, i=0, icg=0, nicg=0, l=0, total=0
cell areas : b=0.000um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=0.000um^2
hp wire lengths : top=0.000um, trunk=0.000um, leaf=0.000um, total=0.000um
Computing max distances from locked parents...
Computing distance_from_locked_parent_restrictions for 0 nodes driven by 0 locked parents
Computing max distances from locked parents done.
Initialize for clustering done. (took cpu=0:00:00.0 real=0:00:00.0)
Bottom-up phase...
Clustering clock_tree clk...
Clustering clock_tree clk done.
Clock DAG stats after bottom-up phase:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1833.720um, total=1833.720um
Clock DAG library cell distribution after bottom-up phase {count}:
Bufs: CLKBUF_X3: 31
Bottom-up phase done. (took cpu=0:00:02.7 real=0:00:01.3)
Legalizing clock trees...
Resynthesising clock tree into netlist...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Resynthesising clock tree into netlist done.
Commiting net attributes....
Commiting net attributes. done.
Leaving CCOpt scope - ClockRefiner...
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Performing a single pass refine place with checks partially disabled for clock sinks and datapath.
*** Starting refinePlace (0:05:59 mem=2126.5M) ***
Total net bbox length = 9.910e+04 (4.407e+04 5.503e+04) (ext = 1.239e+01)
Move report: Detail placement moves 72 insts, mean move: 1.24 um, max move: 4.25 um
Max move on inst (datapath_inst/decode_inst/decode_RF/REG_ARRAY_IN_reg[23][17]): (57.19, 98.84) --> (60.04, 100.24)
Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM: 2126.5MB
Summary Report:
Instances move: 72 (out of 8550 movable)
Instances flipped: 0
Mean displacement: 1.24 um
Max displacement: 4.25 um (Instance: datapath_inst/decode_inst/decode_RF/REG_ARRAY_IN_reg[23][17]) (57.19, 98.84) -> (60.04, 100.24)
Length: 10 sites, height: 1 rows, site name: FreePDK45_38x28_10R_NP_162NW_34O, cell type: DLH_X1
Total net bbox length = 9.917e+04 (4.411e+04 5.506e+04) (ext = 1.239e+01)
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2126.5MB
*** Finished refinePlace (0:06:00 mem=2126.5M) ***
ClockRefiner summary
All clock instances: Moved 25, flipped 6 and cell swapped 0 (out of a total of 1356).
The largest move was 1.78 um for datapath_inst/decode_inst/decode_RF/REG_i_7/Q_reg[22].
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Leaving CCOpt scope - ClockRefiner done. (took cpu=0:00:01.2 real=0:00:00.8)
Disconnecting clock tree from netlist...
Disconnecting clock tree from netlist done.
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.1 real=0:00:00.0)
Clock tree legalization - Histogram:
====================================
--------------------------------
Movement (um) Number of cells
--------------------------------
(empty table)
--------------------------------
Clock tree legalization - There are no Movements:
=================================================
---------------------------------------------
Movement (um) Desired Achieved Node
location location
---------------------------------------------
(empty table)
---------------------------------------------
Legalizing clock trees done. (took cpu=0:00:01.8 real=0:00:01.2)
Clock DAG stats after 'Clustering':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=72.082fF, leaf=494.573fF, total=566.655fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Clustering': none
Clock DAG primary half-corner transition distribution after 'Clustering':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Clustering' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Clustering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.099, avg=0.088, sd=0.006], skew [0.025 vs 0.042], 100% {0.074, 0.099} (wid=0.025 ws=0.024) (gid=0.080 gs=0.017)
Skew group summary after 'Clustering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.099, avg=0.088, sd=0.006], skew [0.025 vs 0.042], 100% {0.074, 0.099} (wid=0.025 ws=0.024) (gid=0.080 gs=0.017)
Legalizer API calls during this step: 291 succeeded with high effort: 291 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Clustering done. (took cpu=0:00:04.7 real=0:00:02.7)
Looking for fanout violations...
Looking for fanout violations done.
CongRepair After Initial Clustering...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Leaving CCOpt scope - Early Global Route...
Clock implementation routing...
Net route status summary:
Clock: 32 (unrouted=32, trialRouted=0, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
Routing using eGR only...
Early Global Route - eGR only step...
(ccopt eGR): There are 32 nets for routing of which 32 have one or more fixed wires.
(ccopt eGR): Start to route 32 all nets
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 5836 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 5836
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=8897 numIgnoredNets=8865
[NR-eGR] Connected 0 must-join pins/ports
[NR-eGR] There are 32 clock nets ( 32 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 32
[NR-eGR] Rule id: 1 Nets: 0
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 32 net(s) in layer range [3, 4]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 5.051200e+03um
[NR-eGR] Create a new net group with 24 nets and layer range [3, 6]
[NR-eGR] Layer group 2: route 24 net(s) in layer range [3, 6]
[NR-eGR] Early Global Route overflow of layer group 2: 0.00% H + 0.00% V. EstWL: 5.048400e+03um
[NR-eGR] Create a new net group with 24 nets and layer range [3, 8]
[NR-eGR] Layer group 3: route 24 net(s) in layer range [3, 8]
[NR-eGR] Early Global Route overflow of layer group 3: 0.00% H + 0.00% V. EstWL: 5.048400e+03um
[NR-eGR] Create a new net group with 23 nets and layer range [3, 10]
[NR-eGR] Layer group 4: route 23 net(s) in layer range [3, 10]
[NR-eGR] Early Global Route overflow of layer group 4: 0.00% H + 0.00% V. EstWL: 5.048400e+03um
[NR-eGR] Create a new net group with 6 nets and layer range [2, 10]
[NR-eGR] Layer group 5: route 6 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 5: 0.00% H + 0.00% V. EstWL: 5.874400e+03um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (0) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 0( 0.00%) ( 0.00%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 0( 0.00%) ( 0.00%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 0( 0.00%) ( 0.00%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 2126.52 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 2126.52 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.01 sec, Real: 0.01 sec, Curr Mem: 2126.52 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 2126.52 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.02 sec, Real: 0.01 sec, Curr Mem: 2126.52 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.03 sec, Real: 0.02 sec, Curr Mem: 2126.52 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33470
[NR-eGR] metal2 (2V) length: 3.490501e+04um, number of vias: 42743
[NR-eGR] metal3 (3H) length: 5.952447e+04um, number of vias: 16537
[NR-eGR] metal4 (4V) length: 2.842622e+04um, number of vias: 1492
[NR-eGR] metal5 (5H) length: 6.456080e+03um, number of vias: 1263
[NR-eGR] metal6 (6V) length: 1.385844e+04um, number of vias: 30
[NR-eGR] metal7 (7H) length: 1.379900e+02um, number of vias: 18
[NR-eGR] metal8 (8V) length: 4.267200e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.437349e+05um, number of vias: 95553
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 5.382180e+03um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Report for selected net(s) only.
[NR-eGR] metal1 (1H) length: 0.000000e+00um, number of vias: 1387
[NR-eGR] metal2 (2V) length: 9.412350e+02um, number of vias: 1539
[NR-eGR] metal3 (3H) length: 2.137855e+03um, number of vias: 960
[NR-eGR] metal4 (4V) length: 1.862000e+03um, number of vias: 66
[NR-eGR] metal5 (5H) length: 4.408100e+02um, number of vias: 2
[NR-eGR] metal6 (6V) length: 2.800000e-01um, number of vias: 0
[NR-eGR] metal7 (7H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal8 (8V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 5.382180e+03um, number of vias: 3954
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total routed clock nets wire length: 5.382180e+03um, number of vias: 3954
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 0.75 sec, Real: 0.51 sec, Curr Mem: 1792.52 MB )
Early Global Route - eGR only step done. (took cpu=0:00:00.9 real=0:00:00.7)
Routing using eGR only done.
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=32, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
CCOPT: Done with clock implementation routing.
Clock implementation routing done.
CCOpt: Starting congestion repair using flow wrapper...
Congestion Repair...
Info: Disable timing driven in postCTS congRepair.
Starting congRepair ...
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 4704 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 4704
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 32 Num Prerouted Wires = 5952
[NR-eGR] Read numTotalNets=8897 numIgnoredNets=32
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 0
[NR-eGR] Rule id: 1 Nets: 8865
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8865 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 1.315720e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (1) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 4( 0.02%) ( 0.02%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 6( 0.03%) ( 0.03%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 10( 0.01%) ( 0.01%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
Early Global Route congestion estimation runtime: 0.67 seconds, mem = 1798.6M
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row bins)
Skipped repairing congestion.
[NR-eGR] Started Export DB wires ( Curr Mem: 1798.61 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 1798.61 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.21 sec, Real: 0.08 sec, Curr Mem: 1798.61 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 1798.61 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.05 sec, Real: 0.02 sec, Curr Mem: 1798.61 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.27 sec, Real: 0.12 sec, Curr Mem: 1798.61 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33470
[NR-eGR] metal2 (2V) length: 3.459882e+04um, number of vias: 42702
[NR-eGR] metal3 (3H) length: 5.711121e+04um, number of vias: 16602
[NR-eGR] metal4 (4V) length: 2.602006e+04um, number of vias: 2109
[NR-eGR] metal5 (5H) length: 8.648475e+03um, number of vias: 1779
[NR-eGR] metal6 (6V) length: 1.609958e+04um, number of vias: 89
[NR-eGR] metal7 (7H) length: 4.481450e+02um, number of vias: 44
[NR-eGR] metal8 (8V) length: 9.493050e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.438756e+05um, number of vias: 96795
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um
[NR-eGR] --------------------------------------------------------------------------
Early Global Route wiring runtime: 0.33 seconds, mem = 1796.6M
Tdgp not successfully inited but do clear! skip clearing
End of congRepair (cpu=0:00:02.5, real=0:00:01.0)
Congestion Repair done. (took cpu=0:00:02.5 real=0:00:01.1)
CCOpt: Starting congestion repair using flow wrapper done.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Leaving CCOpt scope - Early Global Route done. (took cpu=0:00:03.7 real=0:00:02.0)
Leaving CCOpt scope - extractRC...
Updating RC parasitics by calling: "extractRC -noRouteCheck"...
Extraction called for design 'DLX' of instances=8550 and nets=16755 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.4 Real Time: 0:00:01.0 MEM: 1796.613M)
Updating RC parasitics by calling: "extractRC -noRouteCheck" done.
Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.4 real=0:00:00.4)
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.2 real=0:00:00.0)
Clock DAG stats after clustering cong repair call:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after clustering cong repair call: none
Clock DAG primary half-corner transition distribution after clustering cong repair call:
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after clustering cong repair call {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after clustering cong repair call:
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098, avg=0.088, sd=0.006], skew [0.024 vs 0.042], 100% {0.074, 0.098} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Skew group summary after clustering cong repair call:
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098, avg=0.088, sd=0.006], skew [0.024 vs 0.042], 100% {0.074, 0.098} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
CongRepair After Initial Clustering done. (took cpu=0:00:04.5 real=0:00:02.7)
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Stage::Clustering done. (took cpu=0:00:09.3 real=0:00:05.4)
Stage::DRV Fixing...
Fixing clock tree slew time and max cap violations...
Fixing clock tree overload: ...20% ...40% ...60% ...80% ...100%
Clock DAG stats after 'Fixing clock tree slew time and max cap violations':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Fixing clock tree slew time and max cap violations': none
Clock DAG primary half-corner transition distribution after 'Fixing clock tree slew time and max cap violations':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Fixing clock tree slew time and max cap violations' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Fixing clock tree slew time and max cap violations':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Skew group summary after 'Fixing clock tree slew time and max cap violations':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Fixing clock tree slew time and max cap violations done. (took cpu=0:00:00.1 real=0:00:00.1)
Fixing clock tree slew time and max cap violations - detailed pass...
Fixing clock tree overload: ...20% ...40% ...60% ...80% ...100%
Clock DAG stats after 'Fixing clock tree slew time and max cap violations - detailed pass':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Fixing clock tree slew time and max cap violations - detailed pass': none
Clock DAG primary half-corner transition distribution after 'Fixing clock tree slew time and max cap violations - detailed pass':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Fixing clock tree slew time and max cap violations - detailed pass' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Fixing clock tree slew time and max cap violations - detailed pass':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098, avg=0.088, sd=0.006], skew [0.024 vs 0.042], 100% {0.074, 0.098} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Skew group summary after 'Fixing clock tree slew time and max cap violations - detailed pass':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098, avg=0.088, sd=0.006], skew [0.024 vs 0.042], 100% {0.074, 0.098} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Fixing clock tree slew time and max cap violations - detailed pass done. (took cpu=0:00:00.1 real=0:00:00.1)
Stage::DRV Fixing done. (took cpu=0:00:00.2 real=0:00:00.2)
Stage::Insertion Delay Reduction...
Removing unnecessary root buffering...
Clock DAG stats after 'Removing unnecessary root buffering':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Removing unnecessary root buffering': none
Clock DAG primary half-corner transition distribution after 'Removing unnecessary root buffering':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Removing unnecessary root buffering' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Removing unnecessary root buffering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Skew group summary after 'Removing unnecessary root buffering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Removing unnecessary root buffering done. (took cpu=0:00:00.0 real=0:00:00.0)
Removing unconstrained drivers...
Clock DAG stats after 'Removing unconstrained drivers':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Removing unconstrained drivers': none
Clock DAG primary half-corner transition distribution after 'Removing unconstrained drivers':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Removing unconstrained drivers' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Removing unconstrained drivers':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Skew group summary after 'Removing unconstrained drivers':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Removing unconstrained drivers done. (took cpu=0:00:00.0 real=0:00:00.0)
Reducing insertion delay 1...
Clock DAG stats after 'Reducing insertion delay 1':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Reducing insertion delay 1': none
Clock DAG primary half-corner transition distribution after 'Reducing insertion delay 1':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Reducing insertion delay 1' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Reducing insertion delay 1':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Skew group summary after 'Reducing insertion delay 1':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Legalizer API calls during this step: 3 succeeded with high effort: 3 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reducing insertion delay 1 done. (took cpu=0:00:00.3 real=0:00:00.3)
Removing longest path buffering...
Clock DAG stats after 'Removing longest path buffering':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.759fF, leaf=492.734fF, total=564.493fF
wire lengths : top=0.000um, trunk=726.298um, leaf=4467.566um, total=5193.864um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Removing longest path buffering': none
Clock DAG primary half-corner transition distribution after 'Removing longest path buffering':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Removing longest path buffering' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Removing longest path buffering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Skew group summary after 'Removing longest path buffering':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.098], skew [0.024 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Removing longest path buffering done. (took cpu=0:00:00.0 real=0:00:00.0)
Reducing insertion delay 2...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Clock DAG stats after 'Reducing insertion delay 2':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Reducing insertion delay 2': none
Clock DAG primary half-corner transition distribution after 'Reducing insertion delay 2':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Reducing insertion delay 2' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Reducing insertion delay 2':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Skew group summary after 'Reducing insertion delay 2':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Legalizer API calls during this step: 44 succeeded with high effort: 44 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reducing insertion delay 2 done. (took cpu=0:00:00.6 real=0:00:00.6)
Stage::Insertion Delay Reduction done. (took cpu=0:00:01.0 real=0:00:01.0)
CCOpt::Phase::Construction done. (took cpu=0:00:10.5 real=0:00:06.6)
CCOpt::Phase::Implementation...
Stage::Reducing Power...
Improving clock tree routing...
Iteration 1...
Iteration 1 done.
Clock DAG stats after 'Improving clock tree routing':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Improving clock tree routing': none
Clock DAG primary half-corner transition distribution after 'Improving clock tree routing':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Improving clock tree routing' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Improving clock tree routing':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Improving clock tree routing':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Improving clock tree routing done. (took cpu=0:00:00.0 real=0:00:00.0)
Reducing clock tree power 1...
Resizing gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
100%
Clock DAG stats after 'Reducing clock tree power 1':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Reducing clock tree power 1': none
Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 1':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Reducing clock tree power 1' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Reducing clock tree power 1':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Reducing clock tree power 1':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 62 succeeded with high effort: 62 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reducing clock tree power 1 done. (took cpu=0:00:00.2 real=0:00:00.2)
Reducing clock tree power 2...
Clock DAG stats after 'Reducing clock tree power 2':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Reducing clock tree power 2': none
Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 2':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Reducing clock tree power 2' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Reducing clock tree power 2':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Skew group summary after 'Reducing clock tree power 2':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reducing clock tree power 2 done. (took cpu=0:00:00.1 real=0:00:00.1)
Stage::Reducing Power done. (took cpu=0:00:00.4 real=0:00:00.4)
Stage::Balancing...
Approximately balancing fragments step...
Resolve constraints - Approximately balancing fragments...
Resolving skew group constraints...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Solving LP: 1 skew groups; 2 fragments, 2 fraglets and 3 vertices; 25 variables and 66 constraints; tolerance 1
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Resolving skew group constraints done.
Resolve constraints - Approximately balancing fragments done. (took cpu=0:00:00.3 real=0:00:00.3)
Estimate delay to be added in balancing - Approximately balancing fragments...
Trial balancer estimated the amount of delay to be added in balancing: 0.000ns
Estimate delay to be added in balancing - Approximately balancing fragments done. (took cpu=0:00:00.1 real=0:00:00.1)
Approximately balancing fragments...
Moving gates to improve sub-tree skew...
Tried: 33 Succeeded: 0
Topology Tried: 0 Succeeded: 0
0 Succeeded with SS ratio
0 Succeeded with Lollipop: 0 with tier one, 0 with tier two.
Total reducing skew: 0 Average reducing skew for 0 nets : 0
Clock DAG stats after 'Moving gates to improve sub-tree skew':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Moving gates to improve sub-tree skew': none
Clock DAG primary half-corner transition distribution after 'Moving gates to improve sub-tree skew':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Moving gates to improve sub-tree skew' {count}:
Bufs: CLKBUF_X3: 31
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to improve sub-tree skew done. (took cpu=0:00:00.1 real=0:00:00.1)
Approximately balancing fragments bottom up...
bottom up balancing: ...20% ...40% ...60% ...80% ...100%
Clock DAG stats after 'Approximately balancing fragments bottom up':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Approximately balancing fragments bottom up': none
Clock DAG primary half-corner transition distribution after 'Approximately balancing fragments bottom up':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Approximately balancing fragments bottom up' {count}:
Bufs: CLKBUF_X3: 31
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Approximately balancing fragments bottom up done. (took cpu=0:00:00.2 real=0:00:00.2)
Approximately balancing fragments, wire and cell delays...
Approximately balancing fragments, wire and cell delays, iteration 1...
Clock DAG stats after Approximately balancing fragments, wire and cell delays, iteration 1:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after Approximately balancing fragments, wire and cell delays, iteration 1: none
Clock DAG primary half-corner transition distribution after Approximately balancing fragments, wire and cell delays, iteration 1:
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after Approximately balancing fragments, wire and cell delays, iteration 1 {count}:
Bufs: CLKBUF_X3: 31
Approximately balancing fragments, wire and cell delays, iteration 1 done.
Approximately balancing fragments, wire and cell delays done. (took cpu=0:00:00.1 real=0:00:00.1)
Approximately balancing fragments done.
Clock DAG stats after 'Approximately balancing fragments step':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Approximately balancing fragments step': none
Clock DAG primary half-corner transition distribution after 'Approximately balancing fragments step':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Approximately balancing fragments step' {count}:
Bufs: CLKBUF_X3: 31
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Approximately balancing fragments step done. (took cpu=0:00:00.8 real=0:00:00.8)
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Clock DAG stats after Approximately balancing fragments:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after Approximately balancing fragments: none
Clock DAG primary half-corner transition distribution after Approximately balancing fragments:
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after Approximately balancing fragments {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after Approximately balancing fragments:
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after Approximately balancing fragments:
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Improving fragments clock skew...
Clock DAG stats after 'Improving fragments clock skew':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Improving fragments clock skew': none
Clock DAG primary half-corner transition distribution after 'Improving fragments clock skew':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Improving fragments clock skew' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Improving fragments clock skew':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Improving fragments clock skew':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Improving fragments clock skew done. (took cpu=0:00:00.1 real=0:00:00.1)
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Approximately balancing step...
Resolve constraints - Approximately balancing...
Resolving skew group constraints...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (EMS-27): Message (IMPCCOPT-1261) has exceeded the current message display limit of 20.
To increase the message display limit, refer to the product command reference manual.
Solving LP: 1 skew groups; 2 fragments, 2 fraglets and 3 vertices; 25 variables and 66 constraints; tolerance 1
Resolving skew group constraints done.
Resolve constraints - Approximately balancing done. (took cpu=0:00:00.1 real=0:00:00.1)
Approximately balancing...
Approximately balancing, wire and cell delays...
Approximately balancing, wire and cell delays, iteration 1...
Clock DAG stats after Approximately balancing, wire and cell delays, iteration 1:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after Approximately balancing, wire and cell delays, iteration 1: none
Clock DAG primary half-corner transition distribution after Approximately balancing, wire and cell delays, iteration 1:
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after Approximately balancing, wire and cell delays, iteration 1 {count}:
Bufs: CLKBUF_X3: 31
Approximately balancing, wire and cell delays, iteration 1 done.
Approximately balancing, wire and cell delays done. (took cpu=0:00:00.1 real=0:00:00.1)
Approximately balancing done.
Clock DAG stats after 'Approximately balancing step':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Approximately balancing step': none
Clock DAG primary half-corner transition distribution after 'Approximately balancing step':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Approximately balancing step' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Approximately balancing step':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Approximately balancing step':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Approximately balancing step done. (took cpu=0:00:00.3 real=0:00:00.3)
Fixing clock tree overload...
Fixing clock tree overload: ...20% ...40% ...60% ...80% ...100%
Clock DAG stats after 'Fixing clock tree overload':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Fixing clock tree overload': none
Clock DAG primary half-corner transition distribution after 'Fixing clock tree overload':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Fixing clock tree overload' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Fixing clock tree overload':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Fixing clock tree overload':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Fixing clock tree overload done. (took cpu=0:00:00.0 real=0:00:00.0)
Approximately balancing paths...
Added 0 buffers.
Clock DAG stats after 'Approximately balancing paths':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Approximately balancing paths': none
Clock DAG primary half-corner transition distribution after 'Approximately balancing paths':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Approximately balancing paths' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Approximately balancing paths':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Skew group summary after 'Approximately balancing paths':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.079 gs=0.017)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Approximately balancing paths done. (took cpu=0:00:00.1 real=0:00:00.1)
Stage::Balancing done. (took cpu=0:00:01.4 real=0:00:01.4)
Stage::Polishing...
Merging balancing drivers for power...
Tried: 33 Succeeded: 0
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.1 real=0:00:00.0)
Clock DAG stats after 'Merging balancing drivers for power':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Merging balancing drivers for power': none
Clock DAG primary half-corner transition distribution after 'Merging balancing drivers for power':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Merging balancing drivers for power' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Merging balancing drivers for power':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Skew group summary after 'Merging balancing drivers for power':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097], skew [0.023 vs 0.042]
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Merging balancing drivers for power done. (took cpu=0:00:00.2 real=0:00:00.1)
Improving clock skew...
Clock DAG stats after 'Improving clock skew':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=71.282fF, leaf=492.393fF, total=563.675fF
wire lengths : top=0.000um, trunk=718.368um, leaf=4463.282um, total=5181.650um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1836.260um, total=1836.260um
Clock DAG net violations after 'Improving clock skew': none
Clock DAG primary half-corner transition distribution after 'Improving clock skew':
Trunk : target=0.050ns count=1 avg=0.016ns sd=0.000ns min=0.016ns max=0.016ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.003ns min=0.036ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 20 <= 0.048ns, 6 <= 0.050ns}
Clock DAG library cell distribution after 'Improving clock skew' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Improving clock skew':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.080 gs=0.017)
Skew group summary after 'Improving clock skew':
skew_group clk/coherent-synthesis: insertion delay [min=0.074, max=0.097, avg=0.088, sd=0.006], skew [0.023 vs 0.042], 100% {0.074, 0.097} (wid=0.025 ws=0.024) (gid=0.080 gs=0.017)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Improving clock skew done. (took cpu=0:00:00.1 real=0:00:00.1)
Moving gates to reduce wire capacitance...
Modified slew target multipliers. Leaf=(1 to 0.9) Trunk=(1 to 0.95) Top=(1 to 0.95)
Iteration 1...
Artificially removing short and long paths...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Artificially removing short and long paths done. (took cpu=0:00:00.1 real=0:00:00.1)
Moving gates to reduce wire capacitance - iteration 1: WireCapReduction...
Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
Legalizer API calls during this step: 230 succeeded with high effort: 230 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to reduce wire capacitance - iteration 1: WireCapReduction done. (took cpu=0:00:00.6 real=0:00:00.6)
Moving gates to reduce wire capacitance - iteration 1: MoveGates...
Moving gates: Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
...20% ...40% ...60% ...80% ...100%
Legalizer API calls during this step: 434 succeeded with high effort: 434 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to reduce wire capacitance - iteration 1: MoveGates done. (took cpu=0:00:07.7 real=0:00:03.9)
Iteration 1 done.
Iteration 2...
Artificially removing short and long paths...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Artificially removing short and long paths done. (took cpu=0:00:00.0 real=0:00:00.0)
Moving gates to reduce wire capacitance - iteration 2: WireCapReduction...
Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
Legalizer API calls during this step: 181 succeeded with high effort: 181 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to reduce wire capacitance - iteration 2: WireCapReduction done. (took cpu=0:00:01.3 real=0:00:00.6)
Moving gates to reduce wire capacitance - iteration 2: MoveGates...
Moving gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
100%
Legalizer API calls during this step: 434 succeeded with high effort: 434 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to reduce wire capacitance - iteration 2: MoveGates done. (took cpu=0:00:02.6 real=0:00:02.5)
Iteration 2 done.
Reverted slew target multipliers. Leaf=(0.9 to 1) Trunk=(0.95 to 1) Top=(0.95 to 1)
Clock DAG stats after 'Moving gates to reduce wire capacitance':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=62.877fF, leaf=487.443fF, total=550.320fF
wire lengths : top=0.000um, trunk=633.558um, leaf=4420.467um, total=5054.025um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1860.520um, total=1860.520um
Clock DAG net violations after 'Moving gates to reduce wire capacitance': none
Clock DAG primary half-corner transition distribution after 'Moving gates to reduce wire capacitance':
Trunk : target=0.050ns count=1 avg=0.015ns sd=0.000ns min=0.015ns max=0.015ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 19 <= 0.048ns, 7 <= 0.050ns}
Clock DAG library cell distribution after 'Moving gates to reduce wire capacitance' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Moving gates to reduce wire capacitance':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Skew group summary after 'Moving gates to reduce wire capacitance':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Legalizer API calls during this step: 1279 succeeded with high effort: 1279 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Moving gates to reduce wire capacitance done. (took cpu=0:00:12.4 real=0:00:07.9)
Reducing clock tree power 3...
Artificially removing short and long paths...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Artificially removing short and long paths done. (took cpu=0:00:00.0 real=0:00:00.0)
Initial gate capacitance is (rise=1337.648fF fall=1205.303fF).
Resizing gates: ...20% ...40% ...60% ...80% ...Legalizing clock trees...
Legalizing clock trees done. (took cpu=0:00:00.0 real=0:00:00.0)
100%
Clock DAG stats after 'Reducing clock tree power 3':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=62.877fF, leaf=487.443fF, total=550.320fF
wire lengths : top=0.000um, trunk=633.558um, leaf=4420.467um, total=5054.025um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1860.520um, total=1860.520um
Clock DAG net violations after 'Reducing clock tree power 3': none
Clock DAG primary half-corner transition distribution after 'Reducing clock tree power 3':
Trunk : target=0.050ns count=1 avg=0.015ns sd=0.000ns min=0.015ns max=0.015ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 19 <= 0.048ns, 7 <= 0.050ns}
Clock DAG library cell distribution after 'Reducing clock tree power 3' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Reducing clock tree power 3':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Skew group summary after 'Reducing clock tree power 3':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Legalizer API calls during this step: 62 succeeded with high effort: 62 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reducing clock tree power 3 done. (took cpu=0:00:00.3 real=0:00:00.3)
Improving insertion delay...
Clock DAG stats after 'Improving insertion delay':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=62.877fF, leaf=487.443fF, total=550.320fF
wire lengths : top=0.000um, trunk=633.558um, leaf=4420.467um, total=5054.025um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1860.520um, total=1860.520um
Clock DAG net violations after 'Improving insertion delay': none
Clock DAG primary half-corner transition distribution after 'Improving insertion delay':
Trunk : target=0.050ns count=1 avg=0.015ns sd=0.000ns min=0.015ns max=0.015ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 4 <= 0.045ns, 19 <= 0.048ns, 7 <= 0.050ns}
Clock DAG library cell distribution after 'Improving insertion delay' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Improving insertion delay':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Skew group summary after 'Improving insertion delay':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.097, avg=0.087, sd=0.006], skew [0.025 vs 0.042], 100% {0.071, 0.097} (wid=0.025 ws=0.023) (gid=0.079 gs=0.018)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Improving insertion delay done. (took cpu=0:00:00.1 real=0:00:00.1)
Wire Opt OverFix...
Wire Reduction extra effort...
Modified slew target multipliers. Leaf=(1 to 0.95) Trunk=(1 to 1) Top=(1 to 1)
Artificially removing short and long paths...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Artificially removing short and long paths done. (took cpu=0:00:00.0 real=0:00:00.0)
Global shorten wires A0...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Global shorten wires A0 done. (took cpu=0:00:00.0 real=0:00:00.0)
Move For Wirelength - core...
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=2, computed=29, moveTooSmall=18, resolved=0, predictFail=4, currentlyIllegal=0, legalizationFail=1, legalizedMoveTooSmall=2, ignoredLeafDriver=0, worse=131, accepted=7
Max accepted move=14.910um, total accepted move=48.720um, average move=6.960um
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=2, computed=29, moveTooSmall=18, resolved=0, predictFail=4, currentlyIllegal=0, legalizationFail=0, legalizedMoveTooSmall=0, ignoredLeafDriver=0, worse=133, accepted=7
Max accepted move=10.140um, total accepted move=38.890um, average move=5.556um
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=2, computed=29, moveTooSmall=18, resolved=0, predictFail=5, currentlyIllegal=0, legalizationFail=0, legalizedMoveTooSmall=0, ignoredLeafDriver=0, worse=128, accepted=5
Max accepted move=8.050um, total accepted move=28.370um, average move=5.674um
Legalizer API calls during this step: 427 succeeded with high effort: 427 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Move For Wirelength - core done. (took cpu=0:00:01.8 real=0:00:01.8)
Global shorten wires A1...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Global shorten wires A1 done. (took cpu=0:00:00.0 real=0:00:00.0)
Move For Wirelength - core...
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=26, computed=5, moveTooSmall=52, resolved=0, predictFail=0, currentlyIllegal=0, legalizationFail=0, legalizedMoveTooSmall=1, ignoredLeafDriver=0, worse=5, accepted=1
Max accepted move=1.400um, total accepted move=1.400um, average move=1.400um
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=26, computed=5, moveTooSmall=53, resolved=0, predictFail=0, currentlyIllegal=0, legalizationFail=0, legalizedMoveTooSmall=1, ignoredLeafDriver=0, worse=5, accepted=0
Max accepted move=0.000um, total accepted move=0.000um
Legalizer API calls during this step: 13 succeeded with high effort: 13 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Move For Wirelength - core done. (took cpu=0:00:00.1 real=0:00:00.1)
Global shorten wires B...
Legalizer API calls during this step: 144 succeeded with high effort: 144 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Global shorten wires B done. (took cpu=0:00:00.3 real=0:00:00.3)
Move For Wirelength - branch...
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=0, computed=31, moveTooSmall=0, resolved=0, predictFail=0, currentlyIllegal=0, legalizationFail=1, legalizedMoveTooSmall=0, ignoredLeafDriver=0, worse=34, accepted=2
Max accepted move=0.760um, total accepted move=0.950um, average move=0.475um
Move for wirelength. considered=32, filtered=32, permitted=31, cannotCompute=29, computed=2, moveTooSmall=0, resolved=0, predictFail=59, currentlyIllegal=0, legalizationFail=0, legalizedMoveTooSmall=0, ignoredLeafDriver=0, worse=2, accepted=0
Max accepted move=0.000um, total accepted move=0.000um
Legalizer API calls during this step: 39 succeeded with high effort: 39 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Move For Wirelength - branch done. (took cpu=0:00:00.1 real=0:00:00.1)
Reverted slew target multipliers. Leaf=(0.95 to 1) Trunk=(1 to 1) Top=(1 to 1)
Clock DAG stats after 'Wire Reduction extra effort':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=56.905fF, leaf=488.788fF, total=545.693fF
wire lengths : top=0.000um, trunk=568.700um, leaf=4434.631um, total=5003.331um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'Wire Reduction extra effort': none
Clock DAG primary half-corner transition distribution after 'Wire Reduction extra effort':
Trunk : target=0.050ns count=1 avg=0.015ns sd=0.000ns min=0.015ns max=0.015ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after 'Wire Reduction extra effort' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Wire Reduction extra effort':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.096, avg=0.086, sd=0.006], skew [0.024 vs 0.042], 100% {0.071, 0.096} (wid=0.023 ws=0.021) (gid=0.079 gs=0.018)
Skew group summary after 'Wire Reduction extra effort':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.096, avg=0.086, sd=0.006], skew [0.024 vs 0.042], 100% {0.071, 0.096} (wid=0.023 ws=0.021) (gid=0.079 gs=0.018)
Legalizer API calls during this step: 623 succeeded with high effort: 623 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Wire Reduction extra effort done. (took cpu=0:00:02.6 real=0:00:02.6)
Optimizing orientation...
FlipOpt...
Disconnecting clock tree from netlist...
Disconnecting clock tree from netlist done.
Performing Single Threaded FlipOpt
Optimizing orientation on clock cells...
Orientation Wirelength Optimization: Attempted = 33 , Succeeded = 1 , Constraints Broken = 30 , CannotMove = 2 , Illegal = 0 , Other = 0
Optimizing orientation on clock cells done.
Resynthesising clock tree into netlist...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Resynthesising clock tree into netlist done.
FlipOpt done. (took cpu=0:00:00.3 real=0:00:00.3)
Optimizing orientation done. (took cpu=0:00:00.3 real=0:00:00.3)
Clock DAG stats after 'Wire Opt OverFix':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=56.848fF, leaf=488.788fF, total=545.636fF
wire lengths : top=0.000um, trunk=568.060um, leaf=4434.631um, total=5002.691um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'Wire Opt OverFix': none
Clock DAG primary half-corner transition distribution after 'Wire Opt OverFix':
Trunk : target=0.050ns count=1 avg=0.014ns sd=0.000ns min=0.014ns max=0.014ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after 'Wire Opt OverFix' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'Wire Opt OverFix':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.096, avg=0.086, sd=0.006], skew [0.024 vs 0.042], 100% {0.071, 0.096} (wid=0.023 ws=0.021) (gid=0.079 gs=0.018)
Skew group summary after 'Wire Opt OverFix':
skew_group clk/coherent-synthesis: insertion delay [min=0.071, max=0.096, avg=0.086, sd=0.006], skew [0.024 vs 0.042], 100% {0.071, 0.096} (wid=0.023 ws=0.021) (gid=0.079 gs=0.018)
Legalizer API calls during this step: 623 succeeded with high effort: 623 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Wire Opt OverFix done. (took cpu=0:00:03.0 real=0:00:03.0)
Total capacitance is (rise=1883.284fF fall=1750.939fF), of which (rise=545.636fF fall=545.636fF) is wire, and (rise=1337.648fF fall=1205.303fF) is gate.
Stage::Polishing done. (took cpu=0:00:16.2 real=0:00:11.5)
Stage::Updating netlist...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Setting non-default rules before calling refine place.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Leaving CCOpt scope - ClockRefiner...
Performing Clock Only Refine Place.
*** Starting refinePlace (0:06:25 mem=2097.0M) ***
Total net bbox length = 9.919e+04 (4.413e+04 5.507e+04) (ext = 1.375e+01)
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM: 2097.0MB
Summary Report:
Instances move: 0 (out of 8550 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Total net bbox length = 9.919e+04 (4.413e+04 5.507e+04) (ext = 1.375e+01)
Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM: 2097.0MB
*** Finished refinePlace (0:06:25 mem=2097.0M) ***
ClockRefiner summary
All clock instances: Moved 0, flipped 0 and cell swapped 0 (out of a total of 1356).
Leaving CCOpt scope - ClockRefiner done. (took cpu=0:00:00.2 real=0:00:00.1)
Stage::Updating netlist done. (took cpu=0:00:00.3 real=0:00:00.2)
CCOpt::Phase::Implementation done. (took cpu=0:00:18.2 real=0:00:13.4)
CCOpt::Phase::eGRPC...
eGR Post Conditioning loop iteration 0...
Clock implementation routing...
Leaving CCOpt scope - Routing Tools...
Net route status summary:
Clock: 32 (unrouted=32, trialRouted=0, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
Routing using eGR only...
Early Global Route - eGR only step...
(ccopt eGR): There are 32 nets for routing of which 32 have one or more fixed wires.
(ccopt eGR): Start to route 32 all nets
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 5836 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 5836
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=8897 numIgnoredNets=8865
[NR-eGR] Connected 0 must-join pins/ports
[NR-eGR] There are 32 clock nets ( 32 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 32
[NR-eGR] Rule id: 1 Nets: 0
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 32 net(s) in layer range [3, 4]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 4.901400e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 6]
[NR-eGR] Layer group 2: route 26 net(s) in layer range [3, 6]
[NR-eGR] Early Global Route overflow of layer group 2: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 8]
[NR-eGR] Layer group 3: route 26 net(s) in layer range [3, 8]
[NR-eGR] Early Global Route overflow of layer group 3: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 10]
[NR-eGR] Layer group 4: route 26 net(s) in layer range [3, 10]
[NR-eGR] Early Global Route overflow of layer group 4: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 1 nets and layer range [2, 10]
[NR-eGR] Layer group 5: route 1 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 5: 0.00% H + 0.00% V. EstWL: 5.468400e+03um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (0) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 0( 0.00%) ( 0.00%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 0( 0.00%) ( 0.00%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 0( 0.00%) ( 0.00%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 2097.03 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 2097.03 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.02 sec, Real: 0.01 sec, Curr Mem: 2097.03 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 2097.03 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.00 sec, Real: 0.01 sec, Curr Mem: 2097.03 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.02 sec, Real: 0.02 sec, Curr Mem: 2097.03 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33470
[NR-eGR] metal2 (2V) length: 3.458070e+04um, number of vias: 42682
[NR-eGR] metal3 (3H) length: 5.705624e+04um, number of vias: 16583
[NR-eGR] metal4 (4V) length: 2.594294e+04um, number of vias: 2122
[NR-eGR] metal5 (5H) length: 8.636440e+03um, number of vias: 1779
[NR-eGR] metal6 (6V) length: 1.609958e+04um, number of vias: 89
[NR-eGR] metal7 (7H) length: 4.481450e+02um, number of vias: 44
[NR-eGR] metal8 (8V) length: 9.493050e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.437133e+05um, number of vias: 96769
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 5.219940e+03um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Report for selected net(s) only.
[NR-eGR] metal1 (1H) length: 0.000000e+00um, number of vias: 1387
[NR-eGR] metal2 (2V) length: 9.231100e+02um, number of vias: 1519
[NR-eGR] metal3 (3H) length: 2.082885e+03um, number of vias: 941
[NR-eGR] metal4 (4V) length: 1.784890e+03um, number of vias: 79
[NR-eGR] metal5 (5H) length: 4.287750e+02um, number of vias: 2
[NR-eGR] metal6 (6V) length: 2.800000e-01um, number of vias: 0
[NR-eGR] metal7 (7H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal8 (8V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 5.219940e+03um, number of vias: 3928
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total routed clock nets wire length: 5.219940e+03um, number of vias: 3928
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 0.71 sec, Real: 0.50 sec, Curr Mem: 1809.03 MB )
Early Global Route - eGR only step done. (took cpu=0:00:00.8 real=0:00:00.6)
Set FIXED routing status on 32 net(s)
Routing using eGR only done.
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=32, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
CCOPT: Done with clock implementation routing.
Leaving CCOpt scope - Routing Tools done. (took cpu=0:00:00.9 real=0:00:00.7)
Clock implementation routing done.
Leaving CCOpt scope - extractRC...
Updating RC parasitics by calling: "extractRC -noRouteCheck"...
Extraction called for design 'DLX' of instances=8550 and nets=16755 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.3 Real Time: 0:00:01.0 MEM: 1809.027M)
Updating RC parasitics by calling: "extractRC -noRouteCheck" done.
Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.3 real=0:00:00.4)
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Calling post conditioning for eGRPC...
eGRPC...
eGRPC active optimizations:
- Move Down
- Downsizing before DRV sizing
- DRV fixing with cell sizing
- Move to fanout
- Cloning
Currently running CTS, using active skew data
Reset bufferability constraints...
Resetting previous bufferability status on all nets so that eGRPC will attempt to fix all clock tree violations.
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.2 real=0:00:00.0)
Reset bufferability constraints done. (took cpu=0:00:00.2 real=0:00:00.0)
Clock DAG stats eGRPC initial state:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=58.256fF, leaf=509.542fF, total=567.798fF
wire lengths : top=0.000um, trunk=577.970um, leaf=4641.970um, total=5219.940um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations eGRPC initial state: none
Clock DAG primary half-corner transition distribution eGRPC initial state:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 3 <= 0.045ns, 17 <= 0.048ns, 10 <= 0.050ns}
Clock DAG library cell distribution eGRPC initial state {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups eGRPC initial state:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Skew group summary eGRPC initial state:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
eGRPC Moving buffers...
Violation analysis...
Violation analysis done. (took cpu=0:00:00.0 real=0:00:00.0)
Clock DAG stats after 'eGRPC Moving buffers':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=58.256fF, leaf=509.542fF, total=567.798fF
wire lengths : top=0.000um, trunk=577.970um, leaf=4641.970um, total=5219.940um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'eGRPC Moving buffers': none
Clock DAG primary half-corner transition distribution after 'eGRPC Moving buffers':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 3 <= 0.045ns, 17 <= 0.048ns, 10 <= 0.050ns}
Clock DAG library cell distribution after 'eGRPC Moving buffers' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'eGRPC Moving buffers':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Skew group summary after 'eGRPC Moving buffers':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
eGRPC Moving buffers done. (took cpu=0:00:00.1 real=0:00:00.1)
eGRPC Initial Pass of Downsizing Clock Tree cells...
Artificially removing long paths...
Artificially shortened 7 long paths. The largest offset applied was 0.000ns.
Skew Group Offsets:
----------------------------------------------------------------------------------------------------
Skew Group Num. Num. Offset Max Previous Max. Current Max.
Sinks Offsets Percentile Offset Path Delay Path Delay
----------------------------------------------------------------------------------------------------
clk/coherent-synthesis 1325 7 0.528% 0.000ns 0.089ns 0.088ns
----------------------------------------------------------------------------------------------------
Offsets Histogram:
-------------------------------
From (ns) To (ns) Count
-------------------------------
below 0.000 2
0.000 and above 5
-------------------------------
Mean=0.000ns Median=0.000ns Std.Dev=0.000ns
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Artificially removing long paths done. (took cpu=0:00:00.0 real=0:00:00.0)
Modifying slew-target multiplier from 1 to 0.9
Downsizing prefiltering...
Downsizing prefiltering done.
Downsizing: ...20% ...40% ...60% ...80% ...100%
DoDownSizing Summary : numSized = 0, numUnchanged = 2, numSkippedDueToOther = 0, numSkippedDueToCloseToSlewTarget = 29, numSkippedDueToCloseToSkewTarget = 1
CCOpt-eGRPC Downsizing: considered: 2, tested: 0, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 2, unsuccessful: 0, sized: 0
Reverting slew-target multiplier from 0.9 to 1
Reverting Artificially removing long paths...
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
Reverting Artificially removing long paths done. (took cpu=0:00:00.0 real=0:00:00.0)
Clock DAG stats after 'eGRPC Initial Pass of Downsizing Clock Tree cells':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=58.256fF, leaf=509.542fF, total=567.798fF
wire lengths : top=0.000um, trunk=577.970um, leaf=4641.970um, total=5219.940um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'eGRPC Initial Pass of Downsizing Clock Tree cells': none
Clock DAG primary half-corner transition distribution after 'eGRPC Initial Pass of Downsizing Clock Tree cells':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 3 <= 0.045ns, 17 <= 0.048ns, 10 <= 0.050ns}
Clock DAG library cell distribution after 'eGRPC Initial Pass of Downsizing Clock Tree cells' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'eGRPC Initial Pass of Downsizing Clock Tree cells':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Skew group summary after 'eGRPC Initial Pass of Downsizing Clock Tree cells':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Legalizer API calls during this step: 2 succeeded with high effort: 2 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
eGRPC Initial Pass of Downsizing Clock Tree cells done. (took cpu=0:00:00.2 real=0:00:00.2)
eGRPC Fixing DRVs...
Fixing clock tree DRVs: ...20% ...40% ...60% ...80% ...100%
CCOpt-eGRPC: considered: 32, tested: 32, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 0, unsuccessful: 0, sized: 0
PRO Statistics: Fix DRVs (cell sizing):
=======================================
Cell changes by Net Type:
-------------------------------------------------------------------------------------------------
Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized
-------------------------------------------------------------------------------------------------
top 0 0 0 0 0 0
trunk 0 0 0 0 0 0
leaf 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Total 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%)
Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A
Clock DAG stats after 'eGRPC Fixing DRVs':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=58.256fF, leaf=509.542fF, total=567.798fF
wire lengths : top=0.000um, trunk=577.970um, leaf=4641.970um, total=5219.940um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'eGRPC Fixing DRVs': none
Clock DAG primary half-corner transition distribution after 'eGRPC Fixing DRVs':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 3 <= 0.045ns, 17 <= 0.048ns, 10 <= 0.050ns}
Clock DAG library cell distribution after 'eGRPC Fixing DRVs' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'eGRPC Fixing DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Skew group summary after 'eGRPC Fixing DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
eGRPC Fixing DRVs done. (took cpu=0:00:00.2 real=0:00:00.2)
Reconnecting optimized routes...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Reconnecting optimized routes done. (took cpu=0:00:00.0 real=0:00:00.0)
Violation analysis...
Violation analysis done. (took cpu=0:00:00.0 real=0:00:00.0)
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Set dirty flag on 0 instances, 0 nets
Clock DAG stats before routing clock trees:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=58.256fF, leaf=509.542fF, total=567.798fF
wire lengths : top=0.000um, trunk=577.970um, leaf=4641.970um, total=5219.940um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations before routing clock trees: none
Clock DAG primary half-corner transition distribution before routing clock trees:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 1 <= 0.040ns, 3 <= 0.045ns, 17 <= 0.048ns, 10 <= 0.050ns}
Clock DAG library cell distribution before routing clock trees {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups before routing clock trees:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
Skew group summary before routing clock trees:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.089, avg=0.081, sd=0.004], skew [0.020 vs 0.042], 100% {0.069, 0.089} (wid=0.014 ws=0.013) (gid=0.078 gs=0.018)
eGRPC done.
Calling post conditioning for eGRPC done.
eGR Post Conditioning loop iteration 0 done.
Refine place not called during Post Conditioning. Calling it now the eGR->PC Loop is complete.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Leaving CCOpt scope - ClockRefiner...
Performing Single Pass Refine Place.
*** Starting refinePlace (0:06:27 mem=2062.2M) ***
Total net bbox length = 9.919e+04 (4.413e+04 5.507e+04) (ext = 1.375e+01)
Move report: Detail placement moves 36 insts, mean move: 0.96 um, max move: 2.80 um
Max move on inst (datapath_inst/decode_inst/decode_RF/REG_ARRAY_IN_reg[17][31]): (48.83, 101.64) --> (48.83, 104.44)
Runtime: CPU: 0:00:00.9 REAL: 0:00:00.0 MEM: 2062.2MB
Summary Report:
Instances move: 36 (out of 8550 movable)
Instances flipped: 0
Mean displacement: 0.96 um
Max displacement: 2.80 um (Instance: datapath_inst/decode_inst/decode_RF/REG_ARRAY_IN_reg[17][31]) (48.83, 101.64) -> (48.83, 104.44)
Length: 10 sites, height: 1 rows, site name: FreePDK45_38x28_10R_NP_162NW_34O, cell type: DLH_X1
Violation at original loc: Placement Blockage Violation
Total net bbox length = 9.922e+04 (4.415e+04 5.507e+04) (ext = 1.375e+01)
Runtime: CPU: 0:00:00.9 REAL: 0:00:00.0 MEM: 2062.2MB
*** Finished refinePlace (0:06:28 mem=2062.2M) ***
ClockRefiner summary
All clock instances: Moved 0, flipped 0 and cell swapped 0 (out of a total of 1356).
Leaving CCOpt scope - ClockRefiner done. (took cpu=0:00:01.1 real=0:00:00.7)
CCOpt::Phase::eGRPC done. (took cpu=0:00:03.5 real=0:00:02.7)
CCOpt::Phase::Routing...
Clock implementation routing...
Leaving CCOpt scope - Routing Tools...
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=32, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
Routing using eGR in eGR->NR Step...
Early Global Route - eGR->NR step...
(ccopt eGR): There are 32 nets for routing of which 32 have one or more fixed wires.
(ccopt eGR): Start to route 32 all nets
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 5836 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 5836
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 0 Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=8897 numIgnoredNets=8865
[NR-eGR] Connected 0 must-join pins/ports
[NR-eGR] There are 32 clock nets ( 32 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 32
[NR-eGR] Rule id: 1 Nets: 0
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 32 net(s) in layer range [3, 4]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 4.901400e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 6]
[NR-eGR] Layer group 2: route 26 net(s) in layer range [3, 6]
[NR-eGR] Early Global Route overflow of layer group 2: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 8]
[NR-eGR] Layer group 3: route 26 net(s) in layer range [3, 8]
[NR-eGR] Early Global Route overflow of layer group 3: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 26 nets and layer range [3, 10]
[NR-eGR] Layer group 4: route 26 net(s) in layer range [3, 10]
[NR-eGR] Early Global Route overflow of layer group 4: 0.00% H + 0.00% V. EstWL: 4.900000e+03um
[NR-eGR] Create a new net group with 1 nets and layer range [2, 10]
[NR-eGR] Layer group 5: route 1 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 5: 0.00% H + 0.00% V. EstWL: 5.468400e+03um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (0) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 0( 0.00%) ( 0.00%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 0( 0.00%) ( 0.00%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 0( 0.00%) ( 0.00%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 2062.25 MB )
[NR-eGR] Started Export route guide file ( Curr Mem: 2062.25 MB )
[NR-eGR] Finished Export route guide file ( CPU: 0.12 sec, Real: 0.12 sec, Curr Mem: 2062.25 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 2062.25 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.01 sec, Real: 0.01 sec, Curr Mem: 2062.25 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 2062.25 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.02 sec, Real: 0.01 sec, Curr Mem: 2062.25 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.15 sec, Real: 0.13 sec, Curr Mem: 2062.25 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 0.000000e+00um, number of vias: 33470
[NR-eGR] metal2 (2V) length: 3.458070e+04um, number of vias: 42682
[NR-eGR] metal3 (3H) length: 5.705624e+04um, number of vias: 16583
[NR-eGR] metal4 (4V) length: 2.594294e+04um, number of vias: 2122
[NR-eGR] metal5 (5H) length: 8.636440e+03um, number of vias: 1779
[NR-eGR] metal6 (6V) length: 1.609958e+04um, number of vias: 89
[NR-eGR] metal7 (7H) length: 4.481450e+02um, number of vias: 44
[NR-eGR] metal8 (8V) length: 9.493050e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.437133e+05um, number of vias: 96769
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 5.219940e+03um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Report for selected net(s) only.
[NR-eGR] metal1 (1H) length: 0.000000e+00um, number of vias: 1387
[NR-eGR] metal2 (2V) length: 9.231100e+02um, number of vias: 1519
[NR-eGR] metal3 (3H) length: 2.082885e+03um, number of vias: 941
[NR-eGR] metal4 (4V) length: 1.784890e+03um, number of vias: 79
[NR-eGR] metal5 (5H) length: 4.287750e+02um, number of vias: 2
[NR-eGR] metal6 (6V) length: 2.800000e-01um, number of vias: 0
[NR-eGR] metal7 (7H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal8 (8V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 5.219940e+03um, number of vias: 3928
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total routed clock nets wire length: 5.219940e+03um, number of vias: 3928
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 0.84 sec, Real: 0.59 sec, Curr Mem: 1729.25 MB )
Generated NR early global route guides for clocks to: /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/.rgftMvLOJ
Early Global Route - eGR->NR step done. (took cpu=0:00:01.0 real=0:00:00.8)
Routing using eGR in eGR->NR Step done.
Routing using NR in eGR->NR Step...
CCOPT: Preparing to route 32 clock nets with NanoRoute.
All net are default rule.
Removed pre-existing routes for 32 nets.
Preferred NanoRoute mode settings: Current
-droutePostRouteSpreadWire auto
**WARN: (IMPTCM-77): Option "-routeExpDeterministicMultiThread" for command setNanoRouteMode is obsolete and will be removed in a future release. The obsolete option still works in this release but to avoid this warning and to ensure compatibility with future releases, remove the obsolete option from your script.
#WARNING (NRIF-47) This option supports a feature that is under development and experimental, use at your own risk.
#WARNING (NRIF-47) This option supports a feature that is under development and experimental, use at your own risk.
Clock detailed routing...
NanoRoute...
% Begin globalDetailRoute (date=07/19 02:43:24, mem=1212.8M)
globalDetailRoute
#Start globalDetailRoute on Sat Jul 19 02:43:24 2025
#
#WARNING (NRIG-1303) Congestion map does not match the GCELL grid, clearing map.
#num needed restored net=0
#need_extraction net=0 (total=16755)
#WARNING (NRDB-2005) SPECIAL_NET vdd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#WARNING (NRDB-2005) SPECIAL_NET gnd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#NanoRoute Version 20.11-s130_1 NR200802-2257/20_11-UB
#Skip comparing routing design signature in db-snapshot flow
#Using multithreading with 8 threads.
#Start routing data preparation on Sat Jul 19 02:43:25 2025
#
#Minimum voltage of a net in the design = 0.000.
#Maximum voltage of a net in the design = 1.100.
#Voltage range [0.000 - 1.100] has 16524 nets.
#Voltage range [0.000 - 0.000] has 230 nets.
#Voltage range [1.100 - 1.100] has 1 net.
#Initial pin access analysis.
#Detail pin access analysis.
# metal1 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.13500
# metal2 V Track-Pitch = 0.19000 Line-2-Via Pitch = 0.14000
# metal3 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.14000
# metal4 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal5 H Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal6 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal7 H Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal8 V Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal9 H Track-Pitch = 1.60000 Line-2-Via Pitch = 1.60000
# metal10 V Track-Pitch = 1.68000 Line-2-Via Pitch = 1.60000
#Monitoring time of adding inner blkg by smac
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1232.22 (MB), peak = 1501.76 (MB)
#Regenerating Ggrids automatically.
#Auto generating G-grids with size=15 tracks, using layer metal3's pitch = 0.14000.
#Using automatically generated G-grids.
#Done routing data preparation.
#cpu time = 00:00:02, elapsed time = 00:00:01, memory = 1233.39 (MB), peak = 1501.76 (MB)
#reading routing guides ......
#
#Finished routing data preparation on Sat Jul 19 02:43:25 2025
#
#Cpu time = 00:00:02
#Elapsed time = 00:00:01
#Increased memory = 9.20 (MB)
#Total memory = 1233.57 (MB)
#Peak memory = 1501.76 (MB)
#
#
#Start global routing on Sat Jul 19 02:43:25 2025
#
#
#Start global routing initialization on Sat Jul 19 02:43:25 2025
#
#Number of eco nets is 0
#
#Start global routing data preparation on Sat Jul 19 02:43:25 2025
#
#Start routing resource analysis on Sat Jul 19 02:43:25 2025
#
#Routing resource analysis is done on Sat Jul 19 02:43:25 2025
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# metal1 H 1412 0 8930 65.42%
# metal2 V 1049 0 8930 0.00%
# metal3 H 1412 0 8930 0.00%
# metal4 V 712 0 8930 0.00%
# metal5 H 705 0 8930 0.00%
# metal6 V 712 0 8930 0.00%
# metal7 H 235 0 8930 0.00%
# metal8 V 236 0 8930 3.02%
# metal9 H 90 4 8930 8.24%
# metal10 V 72 23 8930 25.06%
# --------------------------------------------------------------
# Total 6635 2.85% 89300 10.17%
#
# 32 nets (0.19%) with 1 preferred extra spacing.
#
#
#
#Global routing data preparation is done on Sat Jul 19 02:43:25 2025
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1238.22 (MB), peak = 1501.76 (MB)
#
#Routing guide is on.
#
#Global routing initialization is done on Sat Jul 19 02:43:25 2025
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1238.37 (MB), peak = 1501.76 (MB)
#
#start global routing iteration 1...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1239.74 (MB), peak = 1501.76 (MB)
#
#start global routing iteration 2...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1239.82 (MB), peak = 1501.76 (MB)
#
#
#Total number of trivial nets (e.g. < 2 pins) = 7831 (skipped).
#Total number of selected nets for routing = 32.
#Total number of unselected nets (but routable) for routing = 8892 (skipped).
#Total number of nets in the design = 16755.
#
#8892 skipped nets do not have any wires.
#32 routable nets have only global wires.
#32 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.)
#
#Routed net constraints summary:
#------------------------------------------------
# Rules Pref Extra Space Unconstrained
#------------------------------------------------
# Default 32 0
#------------------------------------------------
# Total 32 0
#------------------------------------------------
#
#Routing constraints summary of the whole design:
#------------------------------------------------
# Rules Pref Extra Space Unconstrained
#------------------------------------------------
# Default 32 8892
#------------------------------------------------
# Total 32 8892
#------------------------------------------------
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon
# #Gcell %Gcell
# Layer (1) OverCon
# --------------------------------
# metal1 0(0.00%) (0.00%)
# metal2 0(0.00%) (0.00%)
# metal3 0(0.00%) (0.00%)
# metal4 0(0.00%) (0.00%)
# metal5 0(0.00%) (0.00%)
# metal6 0(0.00%) (0.00%)
# metal7 0(0.00%) (0.00%)
# metal8 0(0.00%) (0.00%)
# metal9 0(0.00%) (0.00%)
# metal10 0(0.00%) (0.00%)
# --------------------------------
# Total 0(0.00%) (0.00%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 1
# Overflow after GR: 0.00% H + 0.00% V
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 5017 um.
#Total half perimeter of net bounding box = 2170 um.
#Total wire length on LAYER metal1 = 0 um.
#Total wire length on LAYER metal2 = 678 um.
#Total wire length on LAYER metal3 = 2129 um.
#Total wire length on LAYER metal4 = 1789 um.
#Total wire length on LAYER metal5 = 420 um.
#Total wire length on LAYER metal6 = 0 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 3432
#Up-Via Summary (total 3432):
#
#-----------------------
# metal1 1387
# metal2 1171
# metal3 801
# metal4 73
#-----------------------
# 3432
#
#Total number of involved priority nets 32
#Maximum src to sink distance for priority net 185.1
#Average of max src_to_sink distance for priority net 54.6
#Average of ave src_to_sink distance for priority net 29.9
#Max overcon = 0 track.
#Total overcon = 0.00%.
#Worst layer Gcell overcon rate = 0.00%.
#
#Global routing statistics:
#Cpu time = 00:00:02
#Elapsed time = 00:00:02
#Increased memory = 6.62 (MB)
#Total memory = 1240.20 (MB)
#Peak memory = 1501.76 (MB)
#
#Finished global routing on Sat Jul 19 02:43:27 2025
#
#
#reading routing guides ......
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1239.08 (MB), peak = 1501.76 (MB)
#Start Track Assignment.
#Done with 830 horizontal wires in 3 hboxes and 872 vertical wires in 3 hboxes.
#Done with 809 horizontal wires in 3 hboxes and 857 vertical wires in 3 hboxes.
#Complete Track Assignment.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 5375 um.
#Total half perimeter of net bounding box = 2170 um.
#Total wire length on LAYER metal1 = 356 um.
#Total wire length on LAYER metal2 = 679 um.
#Total wire length on LAYER metal3 = 2066 um.
#Total wire length on LAYER metal4 = 1846 um.
#Total wire length on LAYER metal5 = 428 um.
#Total wire length on LAYER metal6 = 0 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 3432
#Up-Via Summary (total 3432):
#
#-----------------------
# metal1 1387
# metal2 1171
# metal3 801
# metal4 73
#-----------------------
# 3432
#
#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1238.43 (MB), peak = 1501.76 (MB)
#
#Routing data preparation, pin analysis, global routing and track assignment statistics:
#Cpu time = 00:00:05
#Elapsed time = 00:00:03
#Increased memory = 14.14 (MB)
#Total memory = 1238.44 (MB)
#Peak memory = 1501.76 (MB)
#Using multithreading with 8 threads.
#
#Start Detail Routing..
#start initial detail routing ...
# ECO: 3.9% of the total area was rechecked for DRC, and 66.0% required routing.
# number of violations = 0
#cpu time = 00:00:16, elapsed time = 00:00:02, memory = 1259.85 (MB), peak = 1501.76 (MB)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 5229 um.
#Total half perimeter of net bounding box = 2170 um.
#Total wire length on LAYER metal1 = 1 um.
#Total wire length on LAYER metal2 = 225 um.
#Total wire length on LAYER metal3 = 2357 um.
#Total wire length on LAYER metal4 = 2262 um.
#Total wire length on LAYER metal5 = 385 um.
#Total wire length on LAYER metal6 = 0 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 3931
#Up-Via Summary (total 3931):
#
#-----------------------
# metal1 1387
# metal2 1346
# metal3 1143
# metal4 55
#-----------------------
# 3931
#
#Total number of DRC violations = 0
#Cpu time = 00:00:16
#Elapsed time = 00:00:02
#Increased memory = 19.30 (MB)
#Total memory = 1257.73 (MB)
#Peak memory = 1501.76 (MB)
#detailRoute Statistics:
#Cpu time = 00:00:16
#Elapsed time = 00:00:02
#Increased memory = 19.30 (MB)
#Total memory = 1257.74 (MB)
#Peak memory = 1501.76 (MB)
#Skip updating routing design signature in db-snapshot flow
#
#globalDetailRoute statistics:
#Cpu time = 00:00:22
#Elapsed time = 00:00:06
#Increased memory = 55.88 (MB)
#Total memory = 1268.71 (MB)
#Peak memory = 1501.76 (MB)
#Number of warnings = 3
#Total number of warnings = 5
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Sat Jul 19 02:43:31 2025
#
% End globalDetailRoute (date=07/19 02:43:31, total cpu=0:00:22.2, real=0:00:07.0, peak res=1501.8M, current mem=1251.0M)
NanoRoute done. (took cpu=0:00:22.3 real=0:00:06.5)
Clock detailed routing done.
Checking guided vs. routed lengths for 32 nets...
Guided max path lengths
=======================
---------------------------------------
From (um) To (um) Number of paths
---------------------------------------
20.000 40.000 9
40.000 60.000 18
60.000 80.000 3
80.000 100.000 1
100.000 120.000 0
120.000 140.000 0
140.000 160.000 0
160.000 180.000 0
180.000 200.000 1
---------------------------------------
Deviation of routing from guided max path lengths
=================================================
-------------------------------------
From (%) To (%) Number of paths
-------------------------------------
below 0.000 21
0.000 1.000 5
1.000 2.000 2
2.000 3.000 2
3.000 4.000 1
4.000 5.000 0
5.000 6.000 0
6.000 7.000 1
-------------------------------------
Top 10 notable deviations of routed length from guided length
=============================================================
Net datapath_inst/CTS_2 (36 terminals)
Guided length: max path = 72.070um, total = 126.290um
Routed length: max path = 69.190um, total = 136.400um
Deviation: max path = -3.996%, total = 8.005%
Net datapath_inst/decode_inst/decode_RF/CTS_22 (46 terminals)
Guided length: max path = 56.380um, total = 139.140um
Routed length: max path = 51.960um, total = 150.080um
Deviation: max path = -7.840%, total = 7.863%
Net datapath_inst/CTS_3 (40 terminals)
Guided length: max path = 51.350um, total = 123.000um
Routed length: max path = 51.390um, total = 132.290um
Deviation: max path = 0.078%, total = 7.553%
Net datapath_inst/decode_inst/decode_RF/CTS_6 (44 terminals)
Guided length: max path = 46.300um, total = 136.640um
Routed length: max path = 46.710um, total = 146.820um
Deviation: max path = 0.886%, total = 7.450%
Net datapath_inst/CTS_1 (42 terminals)
Guided length: max path = 59.830um, total = 153.144um
Routed length: max path = 60.030um, total = 163.550um
Deviation: max path = 0.334%, total = 6.795%
Net datapath_inst/decode_inst/decode_RF/CTS_23 (46 terminals)
Guided length: max path = 54.940um, total = 129.780um
Routed length: max path = 54.080um, total = 138.120um
Deviation: max path = -1.565%, total = 6.426%
Net datapath_inst/decode_inst/decode_RF/CTS_11 (45 terminals)
Guided length: max path = 54.520um, total = 159.760um
Routed length: max path = 55.310um, total = 169.800um
Deviation: max path = 1.449%, total = 6.284%
Net datapath_inst/CTS_7 (44 terminals)
Guided length: max path = 46.820um, total = 143.524um
Routed length: max path = 47.550um, total = 151.530um
Deviation: max path = 1.559%, total = 5.578%
Net datapath_inst/decode_inst/CTS_1 (47 terminals)
Guided length: max path = 46.980um, total = 147.655um
Routed length: max path = 42.270um, total = 155.770um
Deviation: max path = -10.026%, total = 5.496%
Net datapath_inst/decode_inst/decode_RF/CTS_4 (44 terminals)
Guided length: max path = 39.420um, total = 146.590um
Routed length: max path = 37.670um, total = 154.380um
Deviation: max path = -4.439%, total = 5.314%
Set FIXED routing status on 32 net(s)
Set FIXED placed status on 31 instance(s)
Route Remaining Unrouted Nets...
Running earlyGlobalRoute to complete any remaining unrouted nets.
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
[NR-eGR] Started Early Global Route kernel ( Curr Mem: 1806.57 MB )
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 4704 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 4704
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 32 Num Prerouted Wires = 4604
[NR-eGR] Read numTotalNets=8897 numIgnoredNets=32
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 0
[NR-eGR] Rule id: 1 Nets: 8865
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8865 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 1.315986e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (2) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 4( 0.02%) ( 0.02%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 14( 0.07%) ( 0.07%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 18( 0.01%) ( 0.01%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 1810.70 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 1810.70 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.20 sec, Real: 0.08 sec, Curr Mem: 1810.70 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 1810.70 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.04 sec, Real: 0.01 sec, Curr Mem: 1810.70 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.25 sec, Real: 0.11 sec, Curr Mem: 1810.70 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 1.900000e-01um, number of vias: 33470
[NR-eGR] metal2 (2V) length: 3.456988e+04um, number of vias: 42591
[NR-eGR] metal3 (3H) length: 5.752198e+04um, number of vias: 16625
[NR-eGR] metal4 (4V) length: 2.555786e+04um, number of vias: 2200
[NR-eGR] metal5 (5H) length: 8.365715e+03um, number of vias: 1867
[NR-eGR] metal6 (6V) length: 1.645069e+04um, number of vias: 81
[NR-eGR] metal7 (7H) length: 4.539800e+02um, number of vias: 38
[NR-eGR] metal8 (8V) length: 8.277500e+02um, number of vias: 2
[NR-eGR] metal9 (9H) length: 8.400000e-01um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.437489e+05um, number of vias: 96874
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 2.47 sec, Real: 0.99 sec, Curr Mem: 1806.70 MB )
Route Remaining Unrouted Nets done. (took cpu=0:00:02.6 real=0:00:01.1)
Routing using NR in eGR->NR Step done.
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=32, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
CCOPT: Done with clock implementation routing.
Leaving CCOpt scope - Routing Tools done. (took cpu=0:00:26.0 real=0:00:08.5)
Clock implementation routing done.
Leaving CCOpt scope - extractRC...
Updating RC parasitics by calling: "extractRC -noRouteCheck"...
Extraction called for design 'DLX' of instances=8550 and nets=16755 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.6 Real Time: 0:00:00.0 MEM: 1804.695M)
Updating RC parasitics by calling: "extractRC -noRouteCheck" done.
Leaving CCOpt scope - extractRC done. (took cpu=0:00:00.6 real=0:00:00.7)
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.9 real=0:00:00.2)
Clock DAG stats after routing clock trees:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after routing clock trees: none
Clock DAG primary half-corner transition distribution after routing clock trees:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after routing clock trees {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after routing clock trees:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after routing clock trees:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
CCOpt::Phase::Routing done. (took cpu=0:00:27.7 real=0:00:09.6)
CCOpt::Phase::PostConditioning...
Post Conditioning - Blocking space for clock sinks to ensure they remain legal.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Removing CTS place status from clock tree and sinks.
Switching to inst based legalization.
PostConditioning...
PostConditioning active optimizations:
- DRV fixing with cell sizing and buffering
- Skew fixing with cell sizing
Currently running CTS, using active skew data
Reset bufferability constraints...
Resetting previous bufferability status on all nets so that PostConditioning will attempt to fix all clock tree violations.
Reset bufferability constraints done. (took cpu=0:00:00.0 real=0:00:00.0)
PostConditioning Upsizing To Fix DRVs...
Fixing clock tree DRVs with upsizing: ...20% ...40% ...60% ...80% ...100%
CCOpt-PostConditioning: considered: 32, tested: 32, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 0, unsuccessful: 0, sized: 0
PRO Statistics: Fix DRVs (initial upsizing):
============================================
Cell changes by Net Type:
-------------------------------------------------------------------------------------------------
Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized
-------------------------------------------------------------------------------------------------
top 0 0 0 0 0 0
trunk 0 0 0 0 0 0
leaf 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Total 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%)
Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A
Clock DAG stats after 'PostConditioning Upsizing To Fix DRVs':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'PostConditioning Upsizing To Fix DRVs': none
Clock DAG primary half-corner transition distribution after 'PostConditioning Upsizing To Fix DRVs':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after 'PostConditioning Upsizing To Fix DRVs' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'PostConditioning Upsizing To Fix DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after 'PostConditioning Upsizing To Fix DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
PostConditioning Upsizing To Fix DRVs done. (took cpu=0:00:00.2 real=0:00:00.2)
Recomputing CTS skew targets...
Resolving skew group constraints...
Solving LP: 1 skew groups; 2 fragments, 2 fraglets and 3 vertices; 25 variables and 66 constraints; tolerance 1
Resolving skew group constraints done.
Recomputing CTS skew targets done. (took cpu=0:00:00.4 real=0:00:00.4)
PostConditioning Fixing DRVs...
Fixing clock tree DRVs: ...20% ...40% ...60% ...80% ...100%
CCOpt-PostConditioning: considered: 32, tested: 32, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 0, unsuccessful: 0, sized: 0
PRO Statistics: Fix DRVs (cell sizing):
=======================================
Cell changes by Net Type:
-------------------------------------------------------------------------------------------------
Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized
-------------------------------------------------------------------------------------------------
top 0 0 0 0 0 0
trunk 0 0 0 0 0 0
leaf 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Total 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%)
Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A
Clock DAG stats after 'PostConditioning Fixing DRVs':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'PostConditioning Fixing DRVs': none
Clock DAG primary half-corner transition distribution after 'PostConditioning Fixing DRVs':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after 'PostConditioning Fixing DRVs' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'PostConditioning Fixing DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after 'PostConditioning Fixing DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
PostConditioning Fixing DRVs done. (took cpu=0:00:00.2 real=0:00:00.2)
Buffering to fix DRVs...
Fixing DRVs with route buffering pass 1. Quick buffering: enabled
Rebuffering to fix clock tree DRVs: ...20% ...40% ...60% ...80% ...100%
Inserted 0 buffers and inverters.
success count. Default: 0, QS: 0, QD: 0, FS: 0, MQS: 0
CCOpt-PostConditioning: nets considered: 32, nets tested: 32, nets violation detected: 0, nets violation ignored (due to small violation): 0, nets cannot run: 0, nets attempted: 0, nets unsuccessful: 0, buffered: 0
Clock DAG stats PostConditioning after re-buffering DRV fixing:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations PostConditioning after re-buffering DRV fixing: none
Clock DAG primary half-corner transition distribution PostConditioning after re-buffering DRV fixing:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution PostConditioning after re-buffering DRV fixing {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups PostConditioning after re-buffering DRV fixing:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary PostConditioning after re-buffering DRV fixing:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Buffering to fix DRVs done. (took cpu=0:00:00.2 real=0:00:00.2)
PostConditioning Fixing Skew by cell sizing...
Resized 0 clock insts to decrease delay.
Resized 0 clock insts to increase delay.
PRO Statistics: Fix Skew (cell sizing):
=======================================
Cell changes by Net Type:
-------------------------------------------------------------------------------------------------
Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized
-------------------------------------------------------------------------------------------------
top 0 0 0 0 0 0
trunk 0 0 0 0 0 0
leaf 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Total 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%)
Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A
Clock DAG stats after 'PostConditioning Fixing Skew by cell sizing':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'PostConditioning Fixing Skew by cell sizing': none
Clock DAG primary half-corner transition distribution after 'PostConditioning Fixing Skew by cell sizing':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after 'PostConditioning Fixing Skew by cell sizing' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'PostConditioning Fixing Skew by cell sizing':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after 'PostConditioning Fixing Skew by cell sizing':
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
PostConditioning Fixing Skew by cell sizing done. (took cpu=0:00:00.1 real=0:00:00.1)
Reconnecting optimized routes...
Reset timing graph...
Ignoring AAE DB Resetting ...
Reset timing graph done.
Reconnecting optimized routes done. (took cpu=0:00:00.0 real=0:00:00.0)
Skipping refinePlace: no changes were made during DRV and/or skew fixing steps so it is unnecessary.
Set dirty flag on 0 instances, 0 nets
PostConditioning done.
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=0, fixed=32, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 16723 (unrouted=7858, trialRouted=8865, noStatus=0, routed=0, fixed=0, [crossesIlmBoundary=0, tooFewTerms=7831, (crossesIlmBoundary AND tooFewTerms=0)])
Update timing and DAG stats after post-conditioning...
Update timing and DAG stats after post-conditioning done. (took cpu=0:00:00.0 real=0:00:00.0)
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.7 real=0:00:00.1)
Clock DAG stats after post-conditioning:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after post-conditioning: none
Clock DAG primary half-corner transition distribution after post-conditioning:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after post-conditioning {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after post-conditioning:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after post-conditioning:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
CCOpt::Phase::PostConditioning done. (took cpu=0:00:02.2 real=0:00:01.5)
Setting CTS place status to fixed for clock tree and sinks.
Post-balance tidy up or trial balance steps...
Clock DAG stats at end of CTS:
==============================
------------------------------------------------------------
Cell type Count Area Capacitance
------------------------------------------------------------
Buffers 31 41.230 44.056
Inverters 0 0.000 0.000
Integrated Clock Gates 0 0.000 0.000
Non-Integrated Clock Gates 0 0.000 0.000
Clock Logic 0 0.000 0.000
All 31 41.230 44.056
------------------------------------------------------------
Clock DAG wire lengths at end of CTS:
=====================================
--------------------
Type Wire Length
--------------------
Top 0.000
Trunk 578.110
Leaf 4651.040
Total 5229.150
--------------------
Clock DAG hp wire lengths at end of CTS:
========================================
-----------------------
Type hp Wire Length
-----------------------
Top 0.000
Trunk 0.000
Leaf 1874.495
Total 1874.495
-----------------------
Clock DAG capacitances at end of CTS:
=====================================
----------------------------------------
Type Gate Wire Total
----------------------------------------
Top 0.000 0.000 0.000
Trunk 44.056 57.778 101.834
Leaf 1293.592 500.760 1794.352
Total 1337.648 558.539 1896.187
----------------------------------------
Clock DAG sink capacitances at end of CTS:
==========================================
-----------------------------------------------------------
Count Total Average Std. Dev. Min Max
-----------------------------------------------------------
1325 1293.592 0.976 0.003 0.950 0.977
-----------------------------------------------------------
Clock DAG net violations at end of CTS:
=======================================
None
Clock DAG primary half-corner transition distribution at end of CTS:
====================================================================
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Net Type Target Count Average Std. Dev. Min Max Distribution Over Target
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Trunk 0.050 1 0.008 0.000 0.008 0.008 {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns} -
Leaf 0.050 31 0.046 0.002 0.038 0.049 {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns} -
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Clock DAG library cell distribution at end of CTS:
==================================================
------------------------------------------
Name Type Inst Inst Area
Count (um^2)
------------------------------------------
CLKBUF_X3 buffer 31 41.230
------------------------------------------
Primary reporting skew groups summary at end of CTS:
====================================================
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Half-corner Skew Group Min ID Max ID Skew Skew target Wire skew Worst sink skew Average ID Std.Dev Skew window occupancy
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
std-typ:both.late clk/coherent-synthesis 0.069 0.087 0.018 0.042 0.013 0.005 0.081 0.004 100% {0.069, 0.087}
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Skew group summary at end of CTS:
=================================
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Half-corner Skew Group Min ID Max ID Skew Skew target Wire skew Worst sink skew Average ID Std.Dev Skew window occupancy
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
std-typ:both.late clk/coherent-synthesis 0.069 0.087 0.018 0.042 0.013 0.005 0.081 0.004 100% {0.069, 0.087}
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Found a total of 0 clock tree pins with a slew violation.
Post-balance tidy up or trial balance steps done. (took cpu=0:00:00.1 real=0:00:00.1)
Synthesizing clock trees done.
Tidy Up And Update Timing...
External - Set all clocks to propagated mode...
Innovus updating I/O latencies
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2298.05)
Total number of fetched objects 9940
End delay calculation. (MEM=2637.86 CPU=0:00:01.3 REAL=0:00:00.0)
End delay calculation (fullDC). (MEM=2637.86 CPU=0:00:03.0 REAL=0:00:01.0)
Clock: clk, View: default, Ideal Latency: 0, Propagated Latency: 0.0811465
Executing: set_clock_latency -source -early -max -rise -0.0811465 [get_pins clk]
Clock: clk, View: default, Ideal Latency: 0, Propagated Latency: 0.0811465
Executing: set_clock_latency -source -late -max -rise -0.0811465 [get_pins clk]
Clock: clk, View: default, Ideal Latency: 0, Propagated Latency: 0.0838051
Executing: set_clock_latency -source -early -max -fall -0.0838051 [get_pins clk]
Clock: clk, View: default, Ideal Latency: 0, Propagated Latency: 0.0838051
Executing: set_clock_latency -source -late -max -fall -0.0838051 [get_pins clk]
Setting all clocks to propagated mode.
External - Set all clocks to propagated mode done. (took cpu=0:00:08.6 real=0:00:02.5)
Clock DAG stats after update timingGraph:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=57.778fF, leaf=500.760fF, total=558.539fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4651.040um, total=5229.150um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after update timingGraph: none
Clock DAG primary half-corner transition distribution after update timingGraph:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.046ns sd=0.002ns min=0.038ns max=0.049ns {0 <= 0.030ns, 2 <= 0.040ns, 5 <= 0.045ns, 16 <= 0.048ns, 8 <= 0.050ns}
Clock DAG library cell distribution after update timingGraph {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after update timingGraph:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Skew group summary after update timingGraph:
skew_group clk/coherent-synthesis: insertion delay [min=0.069, max=0.087, avg=0.081, sd=0.004], skew [0.018 vs 0.042], 100% {0.069, 0.087} (wid=0.015 ws=0.013) (gid=0.076 gs=0.016)
Logging CTS constraint violations...
No violations found.
Logging CTS constraint violations done.
Tidy Up And Update Timing done. (took cpu=0:00:09.1 real=0:00:02.9)
Runtime done. (took cpu=0:01:19 real=0:00:40.9)
Runtime Summary
===============
Clock Runtime: (58%) Core CTS 24.01 (Init 2.93, Construction 3.41, Implementation 13.26, eGRPC 1.69, PostConditioning 1.54, Other 1.17)
Clock Runtime: (27%) CTS services 11.15 (RefinePlace 1.59, EarlyGlobalClock 1.68, NanoRoute 6.47, ExtractRC 1.41, TimingAnalysis 0.00)
Clock Runtime: (13%) Other CTS 5.68 (Init 1.05, CongRepair/EGR-DP 2.17, TimingUpdate 2.46, Other 0.00)
Clock Runtime: (100%) Total 40.84
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Synthesizing clock trees with CCOpt done.
**WARN: (IMPSP-9025): No scan chain specified/traced.
Type 'man IMPSP-9025' for more detail.
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 1358.2M, totSessionCpu=0:07:08 **
**INFO: setDesignMode -flowEffort standard -> setting 'setOptMode -allEndPoints true' for the duration of this command.
Need call spDPlaceInit before registerPrioInstLoc.
GigaOpt running with 8 threads.
**optDesign ... cpu = 0:00:03, real = 0:00:01, mem = 1356.0M, totSessionCpu=0:07:11 **
*** optDesign -postCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Hold Target Slack: user slack 0
Setup Target Slack: user slack 0; extra slack 0.0
setUsefulSkewMode -ecoRoute false
No user sequential activity specified, applying default sequential activity of "0.2" for Dynamic Power reporting.
'set_default_switching_activity' finished successfully.
Multi-VT timing optimization disabled based on library information.
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1901.0M)
Footprint cell information for calculating maxBufDist
*info: There are 9 candidate Buffer cells
*info: There are 6 candidate Inverter cells
Compute RC Scale Done ...
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2056.84)
Total number of fetched objects 9940
End delay calculation. (MEM=2287.36 CPU=0:00:08.1 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2287.36 CPU=0:00:09.9 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:13.5 real=0:00:03.0 totSessionCpu=0:07:29 mem=2287.4M)
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.358 | 0.638 | 0.358 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 280 (280) | -2.541 | 280 (280) |
| max_tran | 27 (1279) | -0.778 | 27 (1279) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.893%
------------------------------------------------------------
**optDesign ... cpu = 0:00:22, real = 0:00:09, mem = 1461.4M, totSessionCpu=0:07:30 **
** INFO : this run is activating low effort ccoptDesign flow
*** Starting optimizing excluded clock nets MEM= 1995.4M) ***
*info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 1995.4M) ***
*** Starting optimizing excluded clock nets MEM= 1995.4M) ***
*info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 1995.4M) ***
Info: Done creating the CCOpt slew target map.
Begin: GigaOpt high fanout net optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:07:30.6/0:03:48.2 (2.0), mem = 1995.4M
+----------+---------+--------+--------+------------+--------+
| Density | Commits | WNS | TNS | Real | Mem |
+----------+---------+--------+--------+------------+--------+
| 56.89%| -| 0.000| 0.000| 0:00:00.0| 2211.3M|
| 57.03%| 26| 0.000| 0.000| 0:00:01.0| 2556.5M|
+----------+---------+--------+--------+------------+--------+
*** Finish post-CTS High Fanout Net Fixing (cpu=0:00:02.8 real=0:00:01.0 mem=2556.5M) ***
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
*** DrvOpt [finish] : cpu/real = 0:00:09.2/0:00:06.3 (1.5), totSession cpu/real = 0:07:39.8/0:03:54.4 (2.0), mem = 2348.6M
End: GigaOpt high fanout net optimization
Begin: GigaOpt DRV Optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:07:40.5/0:03:54.8 (2.0), mem = 2348.6M
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| max-tran | max-cap | max-fanout | max-length | setup | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| 167| 6300| -0.82| 316| 316| -0.37| 0| 0| 0| 0| 0.36| 0.00| 0| 0| 0| 57.03| | |
| 0| 0| 0.00| 22| 22| -0.01| 0| 0| 0| 0| 0.64| 0.00| 164| 0| 159| 57.58| 0:00:07.0| 2777.4M|
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.64| 0.00| 16| 0| 6| 57.62| 0:00:01.0| 2777.4M|
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.64| 0.00| 0| 0| 0| 57.62| 0:00:00.0| 2777.4M|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Bottom Preferred Layer:
+---------------+------------+------------+----------+
| Layer | OPT_LA | CLK | Rule |
+---------------+------------+------------+----------+
| metal3 (z=3) | 0 | 32 | default |
| metal4 (z=4) | 7 | 0 | default |
+---------------+------------+------------+----------+
Via Pillar Rule:
None
*** Finish DRV Fixing (cpu=0:00:48.6 real=0:00:08.0 mem=2777.4M) ***
*** Starting refinePlace (0:08:34 mem=2777.4M) ***
Total net bbox length = 1.039e+05 (4.687e+04 5.702e+04) (ext = 1.336e+01)
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8756 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Move report: Detail placement moves 412 insts, mean move: 0.42 um, max move: 2.16 um
Max move on inst (datapath_inst/decode_inst/decode_RF/FE_OFC21_FE_DBTN2_rst): (100.13, 35.84) --> (100.89, 34.44)
Runtime: CPU: 0:00:01.1 REAL: 0:00:00.0 MEM: 2777.4MB
Summary Report:
Instances move: 412 (out of 8725 movable)
Instances flipped: 0
Mean displacement: 0.42 um
Max displacement: 2.16 um (Instance: datapath_inst/decode_inst/decode_RF/FE_OFC21_FE_DBTN2_rst) (100.13, 35.84) -> (100.89, 34.44)
Length: 7 sites, height: 1 rows, site name: FreePDK45_38x28_10R_NP_162NW_34O, cell type: BUF_X4
Total net bbox length = 1.039e+05 (4.689e+04 5.702e+04) (ext = 1.336e+01)
Runtime: CPU: 0:00:01.2 REAL: 0:00:01.0 MEM: 2777.4MB
*** Finished refinePlace (0:08:36 mem=2777.4M) ***
*** maximum move = 2.16 um ***
*** Finished re-routing un-routed nets (2777.4M) ***
*** Finish Physical Update (cpu=0:00:02.4 real=0:00:02.0 mem=2777.4M) ***
*** DrvOpt [finish] : cpu/real = 0:00:56.3/0:00:13.8 (4.1), totSession cpu/real = 0:08:36.7/0:04:08.6 (2.1), mem = 2125.5M
End: GigaOpt DRV Optimization
**optDesign ... cpu = 0:01:29, real = 0:00:30, mem = 1479.0M, totSessionCpu=0:08:37 **
Begin: GigaOpt Global Optimization
*info: use new DP (enabled)
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** SetupOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:08:36.8/0:04:08.7 (2.1), mem = 2111.5M
*info: 32 clock nets excluded
*info: 2 special nets excluded.
*info: 368 no-driver nets excluded.
*info: 32 nets with fixed/cover wires excluded.
** GigaOpt Global Opt WNS Slack 0.000 TNS Slack 0.000
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
| WNS | TNS | Density | Real | Mem |Worst View|Pathgroup| End Point |
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
| 0.000| 0.000| 57.62%| 0:00:00.0| 2319.4M| default| NA| NA |
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
*** Finish post-CTS Global Setup Fixing (cpu=0:00:00.0 real=0:00:00.0 mem=2319.4M) ***
*** Finish post-CTS Setup Fixing (cpu=0:00:00.0 real=0:00:00.0 mem=2319.4M) ***
Bottom Preferred Layer:
+---------------+------------+------------+----------+
| Layer | OPT_LA | CLK | Rule |
+---------------+------------+------------+----------+
| metal3 (z=3) | 0 | 32 | default |
| metal4 (z=4) | 7 | 0 | default |
+---------------+------------+------------+----------+
Via Pillar Rule:
None
** GigaOpt Global Opt End WNS Slack 0.000 TNS Slack 0.000
*** SetupOpt [finish] : cpu/real = 0:00:11.5/0:00:10.9 (1.1), totSession cpu/real = 0:08:48.3/0:04:19.6 (2.0), mem = 2111.5M
End: GigaOpt Global Optimization
*** Timing Is met
*** Check timing (0:00:00.0)
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
Begin: Area Reclaim Optimization
*** AreaOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:08:49.1/0:04:20.4 (2.0), mem = 2317.4M
Usable buffer cells for single buffer setup transform:
CLKBUF_X1 BUF_X1 CLKBUF_X2 BUF_X2 CLKBUF_X3 BUF_X4 BUF_X8 BUF_X16 BUF_X32
Number of usable buffer cells above: 9
Reclaim Optimization WNS Slack 0.030 TNS Slack 0.000 Density 57.62
+----------+---------+--------+--------+------------+--------+
| Density | Commits | WNS | TNS | Real | Mem |
+----------+---------+--------+--------+------------+--------+
| 57.62%| -| 0.030| 0.000| 0:00:00.0| 2317.4M|
| 57.48%| 116| 0.030| 0.000| 0:00:03.0| 2646.6M|
| 57.45%| 14| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.43%| 12| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.42%| 9| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.40%| 7| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.40%| 7| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.40%| 2| 0.030| 0.000| 0:00:00.0| 2646.6M|
| 57.35%| 29| 0.030| 0.000| 0:00:01.0| 2646.6M|
| 57.35%| 1| 0.030| 0.000| 0:00:00.0| 2646.6M|
| 57.35%| 0| 0.030| 0.000| 0:00:00.0| 2646.6M|
| 57.35%| 0| 0.030| 0.000| 0:00:00.0| 2646.6M|
+----------+---------+--------+--------+------------+--------+
Reclaim Optimization End WNS Slack 0.030 TNS Slack 0.000 Density 57.35
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
End: Core Area Reclaim Optimization (cpu = 0:00:51.3) (real = 0:00:11.0) **
*** AreaOpt [finish] : cpu/real = 0:00:50.7/0:00:10.8 (4.7), totSession cpu/real = 0:09:39.9/0:04:31.1 (2.1), mem = 2646.6M
Executing incremental physical updates
Executing incremental physical updates
End: Area Reclaim Optimization (cpu=0:00:51, real=0:00:11, mem=2110.65M, totSessionCpu=0:09:40).
Begin: GigaOpt DRV Optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:09:41.0/0:04:31.6 (2.1), mem = 2110.6M
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| max-tran | max-cap | max-fanout | max-length | setup | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| 2| 66| -0.04| 2| 2| -0.04| 0| 0| 0| 0| 0.64| 0.00| 0| 0| 0| 57.35| | |
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.64| 0.00| 0| 0| 2| 57.35| 0:00:00.0| 2647.8M|
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.64| 0.00| 0| 0| 0| 57.35| 0:00:00.0| 2647.8M|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
*** Finish DRV Fixing (cpu=0:00:01.0 real=0:00:00.0 mem=2647.8M) ***
*** Starting refinePlace (0:09:48 mem=2647.8M) ***
Total net bbox length = 1.032e+05 (4.656e+04 5.665e+04) (ext = 1.336e+01)
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8714 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM: 2647.8MB
Summary Report:
Instances move: 0 (out of 8683 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Total net bbox length = 1.032e+05 (4.656e+04 5.665e+04) (ext = 1.336e+01)
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2647.8MB
*** Finished refinePlace (0:09:48 mem=2647.8M) ***
*** maximum move = 0.00 um ***
*** Finished re-routing un-routed nets (2647.8M) ***
*** Finish Physical Update (cpu=0:00:01.5 real=0:00:01.0 mem=2647.8M) ***
*** DrvOpt [finish] : cpu/real = 0:00:08.0/0:00:05.6 (1.4), totSession cpu/real = 0:09:48.9/0:04:37.2 (2.1), mem = 2439.8M
End: GigaOpt DRV Optimization
------------------------------------------------------------
Summary (cpu=0.13min real=0.08min mem=2112.8M)
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.641 | 0.641 | 0.728 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 57.348%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
**optDesign ... cpu = 0:02:42, real = 0:00:59, mem = 1481.1M, totSessionCpu=0:09:50 **
Active setup views:
default
Dominating endpoints: 0
Dominating TNS: -0.000
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
Begin: Area Reclaim Optimization
*** AreaOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:09:51.7/0:04:39.3 (2.1), mem = 2317.3M
Usable buffer cells for single buffer setup transform:
CLKBUF_X1 BUF_X1 CLKBUF_X2 BUF_X2 CLKBUF_X3 BUF_X4 BUF_X8 BUF_X16 BUF_X32
Number of usable buffer cells above: 9
Reclaim Optimization WNS Slack 0.020 TNS Slack 0.000 Density 57.35
+----------+---------+--------+--------+------------+--------+
| Density | Commits | WNS | TNS | Real | Mem |
+----------+---------+--------+--------+------------+--------+
| 57.35%| -| 0.020| 0.000| 0:00:00.0| 2317.3M|
| 57.12%| 105| 0.020| 0.000| 0:00:02.0| 2703.7M|
| 57.09%| 15| 0.020| 0.000| 0:00:02.0| 2703.7M|
| 57.06%| 12| 0.020| 0.000| 0:00:02.0| 2703.7M|
| 57.04%| 10| 0.020| 0.000| 0:00:01.0| 2703.7M|
| 57.03%| 7| 0.020| 0.000| 0:00:01.0| 2703.7M|
| 57.03%| 0| 0.020| 0.000| 0:00:01.0| 2703.7M|
| 57.02%| 1| 0.020| 0.000| 0:00:00.0| 2703.7M|
| 57.02%| 0| 0.020| 0.000| 0:00:00.0| 2703.7M|
| 57.02%| 0| 0.020| 0.000| 0:00:00.0| 2703.7M|
+----------+---------+--------+--------+------------+--------+
Reclaim Optimization End WNS Slack 0.020 TNS Slack 0.000 Density 57.02
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
End: Core Area Reclaim Optimization (cpu = 0:00:55.4) (real = 0:00:11.0) **
*** Starting refinePlace (0:10:47 mem=2703.7M) ***
Total net bbox length = 9.865e+04 (4.359e+04 5.506e+04) (ext = 1.336e+01)
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8617 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2703.7MB
Summary Report:
Instances move: 0 (out of 8586 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Total net bbox length = 9.865e+04 (4.359e+04 5.506e+04) (ext = 1.336e+01)
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2703.7MB
*** Finished refinePlace (0:10:48 mem=2703.7M) ***
*** maximum move = 0.00 um ***
*** Finished re-routing un-routed nets (2703.7M) ***
*** Finish Physical Update (cpu=0:00:01.9 real=0:00:01.0 mem=2703.7M) ***
*** AreaOpt [finish] : cpu/real = 0:00:56.7/0:00:11.9 (4.8), totSession cpu/real = 0:10:48.4/0:04:51.2 (2.2), mem = 2703.7M
End: Area Reclaim Optimization (cpu=0:00:57, real=0:00:12, mem=2109.70M, totSessionCpu=0:10:49).
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 4704 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 4704
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 32 Num Prerouted Wires = 4604
[NR-eGR] Read numTotalNets=8929 numIgnoredNets=32
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 8897
[NR-eGR] Rule id: 1 Nets: 0
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8897 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.01% V. EstWL: 1.266300e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (2) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 4( 0.02%) ( 0.02%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 18( 0.09%) ( 0.09%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 22( 0.01%) ( 0.01%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 2115.80 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 2115.80 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.21 sec, Real: 0.08 sec, Curr Mem: 2115.80 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 2115.80 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.04 sec, Real: 0.01 sec, Curr Mem: 2115.80 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.26 sec, Real: 0.10 sec, Curr Mem: 2115.80 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 1.900000e-01um, number of vias: 32805
[NR-eGR] metal2 (2V) length: 3.326630e+04um, number of vias: 41489
[NR-eGR] metal3 (3H) length: 5.500283e+04um, number of vias: 16217
[NR-eGR] metal4 (4V) length: 2.519312e+04um, number of vias: 2077
[NR-eGR] metal5 (5H) length: 7.613670e+03um, number of vias: 1800
[NR-eGR] metal6 (6V) length: 1.597818e+04um, number of vias: 81
[NR-eGR] metal7 (7H) length: 5.172750e+02um, number of vias: 42
[NR-eGR] metal8 (8V) length: 9.637950e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.385354e+05um, number of vias: 94511
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 2.63 sec, Real: 1.14 sec, Curr Mem: 2048.28 MB )
Extraction called for design 'DLX' of instances=8617 and nets=9458 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.4 Real Time: 0:00:00.0 MEM: 2046.281M)
Compute RC Scale Done ...
[hotspot] +------------+---------------+---------------+
[hotspot] | | max hotspot | total hotspot |
[hotspot] +------------+---------------+---------------+
[hotspot] | normalized | 0.00 | 0.00 |
[hotspot] +------------+---------------+---------------+
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row bins)
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2040.27)
Total number of fetched objects 10007
End delay calculation. (MEM=2377.27 CPU=0:00:07.7 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2377.27 CPU=0:00:09.0 REAL=0:00:01.0)
Begin: GigaOpt postEco DRV Optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:11:07.2/0:04:57.0 (2.2), mem = 2377.3M
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| max-tran | max-cap | max-fanout | max-length | setup | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| 0| 0| 0.00| 1| 1| -0.00| 0| 0| 0| 0| 0.65| 0.00| 0| 0| 0| 57.02| | |
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.65| 0.00| 0| 0| 1| 57.02| 0:00:00.0| 2617.2M|
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.65| 0.00| 0| 0| 0| 57.02| 0:00:00.0| 2617.2M|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
*** Finish DRV Fixing (cpu=0:00:00.8 real=0:00:00.0 mem=2617.3M) ***
*** DrvOpt [finish] : cpu/real = 0:00:05.6/0:00:04.1 (1.4), totSession cpu/real = 0:11:12.8/0:05:01.0 (2.2), mem = 2409.3M
End: GigaOpt postEco DRV Optimization
Running refinePlace -preserveRouting true -hardFence false
*** Starting refinePlace (0:11:13 mem=2409.3M) ***
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8617 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Starting Small incrNP...
Density distribution unevenness ratio = 8.729%
Skipped incrNP (cpu=0:00:00.0, real=0:00:00.0, mem=2409.3M)
End of Small incrNP (cpu=0:00:00.0, real=0:00:00.0)
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2409.3MB
Summary Report:
Instances move: 0 (out of 8586 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM: 2409.3MB
*** Finished refinePlace (0:11:14 mem=2409.3M) ***
Active setup views:
default
Dominating endpoints: 0
Dominating TNS: -0.000
Extraction called for design 'DLX' of instances=8617 and nets=9458 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.4 Real Time: 0:00:01.0 MEM: 2008.766M)
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2047.25)
Total number of fetched objects 10007
End delay calculation. (MEM=2366.04 CPU=0:00:07.2 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2366.04 CPU=0:00:08.9 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:14.2 real=0:00:03.0 totSessionCpu=0:11:29 mem=2366.0M)
Reported timing to dir ./timingReports
**optDesign ... cpu = 0:04:22, real = 0:01:27, mem = 1503.8M, totSessionCpu=0:11:29 **
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.654 | 0.654 | 0.718 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 57.024%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
**optDesign ... cpu = 0:04:24, real = 0:01:31, mem = 1503.0M, totSessionCpu=0:11:32 **
*** Finished optDesign ***
Info: Destroy the CCOpt slew target map.
Set place::cacheFPlanSiteMark to 0
*** Summary of all messages that are not suppressed in this session:
Severity ID Count Summary
WARNING IMPEXT-3530 5 The process node is not set. Use the com...
WARNING IMPSP-5140 4 Global net connect rules have not been c...
WARNING IMPSP-105 18 'setPlaceMode -maxRouteLayer' will becom...
WARNING IMPSP-315 4 Found %d instances insts with no PG Term...
WARNING IMPSP-9025 1 No scan chain specified/traced.
WARNING IMPCCOPT-1361 3 Routing configuration for %s nets in clo...
WARNING IMPCCOPT-1184 1 The library has no usable balanced %ss f...
WARNING IMPCCOPT-1261 34 The skew target of %s for %s is too smal...
WARNING IMPTCM-77 1 Option "%s" for command %s is obsolete a...
*** Message Summary: 71 warning(s), 0 error(s)
#% End ccopt_design (date=07/19 02:45:09, total cpu=0:05:44, real=0:02:13, peak res=1866.9M, current mem=1416.4M)
<CMD> timeDesign -postCTS -pathReports -drvReports -slackReports -numPaths 10 -prefix DLX_postCTS_setup -outDir ./physical_design/timingReport
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1986.0M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.654 | 0.654 | 0.718 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 57.024%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 5.69 sec
Total Real time: 4.0 sec
Total Memory Usage: 1986.429688 Mbytes
<CMD> timeDesign -postCTS -hold -pathReports -slackReports -numPaths 10 -prefix DLX_postCTS_hold -outDir ./physical_design/timingReport
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1938.9M)
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=1972.52)
Total number of fetched objects 10007
End delay calculation. (MEM=2286.43 CPU=0:00:06.9 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2286.43 CPU=0:00:08.3 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:10.1 real=0:00:02.0 totSessionCpu=0:11:50 mem=2286.4M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Hold views included:
default
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.244 | 0.073 | -0.244 |
| TNS (ns):| -59.324 | 0.000 | -59.324 |
| Violating Paths:| 1172 | 0 | 1172 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
Density: 57.024%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 13.51 sec
Total Real time: 4.0 sec
Total Memory Usage: 1918.917969 Mbytes
<CMD> saveDesign ./physical_design/4_stage_postCTS.enc
#% Begin save design ... (date=07/19 02:45:17, mem=1321.9M)
% Begin Save ccopt configuration ... (date=07/19 02:45:17, mem=1321.9M)
% End Save ccopt configuration ... (date=07/19 02:45:17, total cpu=0:00:00.2, real=0:00:00.0, peak res=1322.9M, current mem=1322.9M)
% Begin Save netlist data ... (date=07/19 02:45:17, mem=1322.9M)
Writing Binary DB to ./physical_design/4_stage_postCTS.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:45:17, total cpu=0:00:00.1, real=0:00:00.0, peak res=1324.8M, current mem=1324.8M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/4_stage_postCTS.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:45:17, mem=1325.5M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:45:17, total cpu=0:00:00.0, real=0:00:00.0, peak res=1325.5M, current mem=1325.5M)
Saving preference file ./physical_design/4_stage_postCTS.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Save Adaptive View Pruning View Names to Binary file
Saving property file ./physical_design/4_stage_postCTS.enc.dat/DLX.prop
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2013.5M) ***
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveRoute (cpu=0:00:00.3 real=0:00:01.0 mem=2005.5M) ***
TAT_INFO: ::saveRoute REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
#Saving pin access data to file ./physical_design/4_stage_postCTS.enc.dat/DLX.apa ...
#
TAT_INFO: ::db::saveSymbolTable REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 1 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:45:19, mem=1325.8M)
% End Save power constraints data ... (date=07/19 02:45:19, total cpu=0:00:00.0, real=0:00:00.0, peak res=1325.8M, current mem=1325.8M)
high standard low
Generated self-contained design 4_stage_postCTS.enc.dat
#% End save design ... (date=07/19 02:45:31, total cpu=0:00:12.9, real=0:00:14.0, peak res=1326.8M, current mem=1326.7M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> optDesign -postCTS
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 1326.7M, totSessionCpu=0:12:04 **
**INFO: User settings:
setExtractRCMode -engine preRoute
setUsefulSkewMode -ecoRoute false
setUsefulSkewMode -maxAllowedDelay 1
setUsefulSkewMode -maxSkew false
setUsefulSkewMode -noBoundary false
setUsefulSkewMode -useCells {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32 CLKBUF_X1 CLKBUF_X2 CLKBUF_X3 INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32}
setDelayCalMode -enable_high_fanout true
setDelayCalMode -eng_copyNetPropToNewNet true
setDelayCalMode -engine aae
setDelayCalMode -ignoreNetLoad false
setDelayCalMode -SIAware false
setOptMode -activeHoldViews { default }
setOptMode -activeSetupViews { default }
setOptMode -autoSetupViews { default}
setOptMode -autoTDGRSetupViews { default}
setOptMode -drcMargin 0
setOptMode -fixDrc true
setOptMode -preserveAllSequential false
setOptMode -setupTargetSlack 0
setPlaceMode -maxRouteLayer 6
setPlaceMode -place_design_floorplan_mode false
setPlaceMode -place_detail_check_route false
setPlaceMode -place_detail_preserve_routing true
setPlaceMode -place_detail_remove_affected_routing false
setPlaceMode -place_detail_swap_eeq_cells false
setPlaceMode -place_global_clock_gate_aware true
setPlaceMode -place_global_cong_effort auto
setPlaceMode -place_global_ignore_scan true
setPlaceMode -place_global_ignore_spare false
setPlaceMode -place_global_module_aware_spare false
setPlaceMode -place_global_place_io_pins true
setPlaceMode -place_global_reorder_scan true
setPlaceMode -powerDriven false
setPlaceMode -timingDriven true
setAnalysisMode -analysisType single
setAnalysisMode -checkType setup
setAnalysisMode -clkSrcPath true
setAnalysisMode -clockPropagation sdcControl
setAnalysisMode -skew true
setAnalysisMode -virtualIPO false
setRouteMode -earlyGlobalHonorMsvRouteConstraint false
setRouteMode -earlyGlobalRoutePartitionPinGuide true
**INFO: setDesignMode -flowEffort standard -> setting 'setOptMode -allEndPoints true' for the duration of this command.
Need call spDPlaceInit before registerPrioInstLoc.
GigaOpt running with 8 threads.
**optDesign ... cpu = 0:00:03, real = 0:00:02, mem = 1349.1M, totSessionCpu=0:12:07 **
*** optDesign -postCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Hold Target Slack: user slack 0
Setup Target Slack: user slack 0; extra slack 0.0
setUsefulSkewMode -ecoRoute false
Multi-VT timing optimization disabled based on library information.
Start to check current routing status for nets...
All nets are already routed correctly.
End to check current routing status for nets (mem=1954.5M)
Compute RC Scale Done ...
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2100.93)
Total number of fetched objects 10007
End delay calculation. (MEM=2334.44 CPU=0:00:07.8 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2334.44 CPU=0:00:09.1 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:12.9 real=0:00:02.0 totSessionCpu=0:12:23 mem=2334.4M)
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.654 | 0.654 | 0.718 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 57.024%
------------------------------------------------------------
**optDesign ... cpu = 0:00:20, real = 0:00:09, mem = 1458.6M, totSessionCpu=0:12:24 **
** INFO : this run is activating low effort ccoptDesign flow
*** Starting optimizing excluded clock nets MEM= 2035.5M) ***
*info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 2035.5M) ***
*** Starting optimizing excluded clock nets MEM= 2035.5M) ***
*info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 2035.5M) ***
Info: Done creating the CCOpt slew target map.
Begin: GigaOpt high fanout net optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:12:24.7/0:05:41.1 (2.2), mem = 2035.5M
*** DrvOpt [finish] : cpu/real = 0:00:06.1/0:00:05.1 (1.2), totSession cpu/real = 0:12:30.8/0:05:46.1 (2.2), mem = 2043.5M
End: GigaOpt high fanout net optimization
Begin: GigaOpt Global Optimization
*info: use new DP (enabled)
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** SetupOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:12:31.5/0:05:46.6 (2.2), mem = 2043.4M
*info: 32 clock nets excluded
*info: 2 special nets excluded.
*info: 494 no-driver nets excluded.
*info: 32 nets with fixed/cover wires excluded.
** GigaOpt Global Opt WNS Slack 0.000 TNS Slack 0.000
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
| WNS | TNS | Density | Real | Mem |Worst View|Pathgroup| End Point |
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
| 0.000| 0.000| 57.02%| 0:00:00.0| 2251.4M| default| NA| NA |
+--------+--------+----------+------------+--------+----------+---------+----------------------------------------------------+
*** Finish post-CTS Global Setup Fixing (cpu=0:00:00.0 real=0:00:00.0 mem=2251.4M) ***
*** Finish post-CTS Setup Fixing (cpu=0:00:00.0 real=0:00:00.0 mem=2251.4M) ***
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
** GigaOpt Global Opt End WNS Slack 0.000 TNS Slack 0.000
*** SetupOpt [finish] : cpu/real = 0:00:11.1/0:00:10.5 (1.0), totSession cpu/real = 0:12:42.6/0:05:57.1 (2.1), mem = 2043.5M
End: GigaOpt Global Optimization
*** Timing Is met
*** Check timing (0:00:00.0)
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
Begin: Area Reclaim Optimization
*** AreaOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:12:44.1/0:05:58.5 (2.1), mem = 2251.9M
Usable buffer cells for single buffer setup transform:
CLKBUF_X1 BUF_X1 CLKBUF_X2 BUF_X2 CLKBUF_X3 BUF_X4 BUF_X8 BUF_X16 BUF_X32
Number of usable buffer cells above: 9
Reclaim Optimization WNS Slack 0.020 TNS Slack 0.000 Density 57.02
+----------+---------+--------+--------+------------+--------+
| Density | Commits | WNS | TNS | Real | Mem |
+----------+---------+--------+--------+------------+--------+
| 57.02%| -| 0.020| 0.000| 0:00:00.0| 2251.9M|
| 56.85%| 79| 0.020| 0.000| 0:00:03.0| 2695.6M|
| 56.83%| 10| 0.020| 0.000| 0:00:02.0| 2695.6M|
| 56.81%| 11| 0.020| 0.000| 0:00:01.0| 2695.6M|
| 56.79%| 9| 0.020| 0.000| 0:00:01.0| 2695.6M|
| 56.78%| 7| 0.020| 0.000| 0:00:01.0| 2695.6M|
| 56.78%| 0| 0.020| 0.000| 0:00:00.0| 2695.6M|
| 56.78%| 1| 0.020| 0.000| 0:00:01.0| 2695.6M|
| 56.78%| 0| 0.020| 0.000| 0:00:00.0| 2695.6M|
| 56.78%| 0| 0.020| 0.000| 0:00:00.0| 2695.6M|
+----------+---------+--------+--------+------------+--------+
Reclaim Optimization End WNS Slack 0.020 TNS Slack 0.000 Density 56.78
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
End: Core Area Reclaim Optimization (cpu = 0:00:54.1) (real = 0:00:11.0) **
*** Starting refinePlace (0:13:38 mem=2695.6M) ***
Total net bbox length = 9.634e+04 (4.239e+04 5.395e+04) (ext = 1.336e+01)
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8563 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2695.6MB
Summary Report:
Instances move: 0 (out of 8532 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Total net bbox length = 9.634e+04 (4.239e+04 5.395e+04) (ext = 1.336e+01)
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2695.6MB
*** Finished refinePlace (0:13:39 mem=2695.6M) ***
*** maximum move = 0.00 um ***
*** Finished re-routing un-routed nets (2695.6M) ***
*** Finish Physical Update (cpu=0:00:02.4 real=0:00:02.0 mem=2695.6M) ***
*** AreaOpt [finish] : cpu/real = 0:00:55.9/0:00:12.1 (4.6), totSession cpu/real = 0:13:40.0/0:06:10.7 (2.2), mem = 2695.6M
End: Area Reclaim Optimization (cpu=0:00:57, real=0:00:13, mem=2050.12M, totSessionCpu=0:13:41).
[NR-eGR] Track table information for default rule:
[NR-eGR] metal1 has no routable track
[NR-eGR] metal2 has single uniform track structure
[NR-eGR] metal3 has single uniform track structure
[NR-eGR] metal4 has single uniform track structure
[NR-eGR] metal5 has single uniform track structure
[NR-eGR] metal6 has single uniform track structure
[NR-eGR] metal7 has single uniform track structure
[NR-eGR] metal8 has single uniform track structure
[NR-eGR] metal9 has single uniform track structure
[NR-eGR] metal10 has single uniform track structure
[NR-eGR] Read 4704 PG shapes
[NR-eGR] #Routing Blockages : 0
[NR-eGR] #Instance Blockages : 0
[NR-eGR] #PG Blockages : 4704
[NR-eGR] #Halo Blockages : 0
[NR-eGR] #Boundary Blockages : 0
[NR-eGR] Num Prerouted Nets = 32 Num Prerouted Wires = 4604
[NR-eGR] Read numTotalNets=8806 numIgnoredNets=32
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0 Nets: 8774
[NR-eGR] Rule id: 1 Nets: 0
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 8774 net(s) in layer range [2, 10]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.01% V. EstWL: 1.238510e+05um
[NR-eGR] Congestion Analysis By layer: (blocked Gcells are excluded)
[NR-eGR] OverCon
[NR-eGR] #Gcell %Gcell
[NR-eGR] Layer (2) OverCon
[NR-eGR] ----------------------------------------------
[NR-eGR] metal1 (1) 0( 0.00%) ( 0.00%)
[NR-eGR] metal2 (2) 4( 0.02%) ( 0.02%)
[NR-eGR] metal3 (3) 0( 0.00%) ( 0.00%)
[NR-eGR] metal4 (4) 12( 0.06%) ( 0.06%)
[NR-eGR] metal5 (5) 0( 0.00%) ( 0.00%)
[NR-eGR] metal6 (6) 0( 0.00%) ( 0.00%)
[NR-eGR] metal7 (7) 0( 0.00%) ( 0.00%)
[NR-eGR] metal8 (8) 0( 0.00%) ( 0.00%)
[NR-eGR] metal9 (9) 0( 0.00%) ( 0.00%)
[NR-eGR] metal10 (10) 0( 0.00%) ( 0.00%)
[NR-eGR] ----------------------------------------------
[NR-eGR] Total 16( 0.01%) ( 0.01%)
[NR-eGR]
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.00% H + 0.00% V
[NR-eGR] Started Export DB wires ( Curr Mem: 2054.20 MB )
[NR-eGR] Started Export all nets (8T) ( Curr Mem: 2054.20 MB )
[NR-eGR] Finished Export all nets (8T) ( CPU: 0.21 sec, Real: 0.07 sec, Curr Mem: 2054.20 MB )
[NR-eGR] Started Set wire vias (8T) ( Curr Mem: 2054.20 MB )
[NR-eGR] Finished Set wire vias (8T) ( CPU: 0.04 sec, Real: 0.01 sec, Curr Mem: 2054.20 MB )
[NR-eGR] Finished Export DB wires ( CPU: 0.26 sec, Real: 0.09 sec, Curr Mem: 2054.20 MB )
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] metal1 (1F) length: 1.900000e-01um, number of vias: 32406
[NR-eGR] metal2 (2V) length: 3.332829e+04um, number of vias: 41063
[NR-eGR] metal3 (3H) length: 5.388608e+04um, number of vias: 15980
[NR-eGR] metal4 (4V) length: 2.474983e+04um, number of vias: 1949
[NR-eGR] metal5 (5H) length: 7.287345e+03um, number of vias: 1679
[NR-eGR] metal6 (6V) length: 1.521451e+04um, number of vias: 70
[NR-eGR] metal7 (7H) length: 4.285350e+02um, number of vias: 34
[NR-eGR] metal8 (8V) length: 7.160300e+02um, number of vias: 0
[NR-eGR] metal9 (9H) length: 0.000000e+00um, number of vias: 0
[NR-eGR] metal10 (10V) length: 0.000000e+00um, number of vias: 0
[NR-eGR] Total length: 1.356108e+05um, number of vias: 93181
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 0.000000e+00um
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Finished Early Global Route kernel ( CPU: 2.61 sec, Real: 1.13 sec, Curr Mem: 2038.68 MB )
Extraction called for design 'DLX' of instances=8563 and nets=9457 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.4 Real Time: 0:00:01.0 MEM: 2036.680M)
Compute RC Scale Done ...
[hotspot] +------------+---------------+---------------+
[hotspot] | | max hotspot | total hotspot |
[hotspot] +------------+---------------+---------------+
[hotspot] | normalized | 0.00 | 0.00 |
[hotspot] +------------+---------------+---------------+
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row bins)
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2101.78)
Total number of fetched objects 9953
End delay calculation. (MEM=2421.57 CPU=0:00:07.3 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2421.57 CPU=0:00:08.6 REAL=0:00:02.0)
Begin: GigaOpt postEco DRV Optimization
Info: 32 nets with fixed/cover wires excluded.
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:13:58.8/0:06:16.4 (2.2), mem = 2421.6M
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| max-tran | max-cap | max-fanout | max-length | setup | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.67| 0.00| 0| 0| 0| 56.78| | |
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.67| 0.00| 0| 0| 0| 56.78| 0:00:00.0| 2661.6M|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
*** Finish DRV Fixing (cpu=0:00:00.6 real=0:00:00.0 mem=2661.6M) ***
*** DrvOpt [finish] : cpu/real = 0:00:05.2/0:00:03.9 (1.3), totSession cpu/real = 0:14:04.0/0:06:20.3 (2.2), mem = 2453.6M
End: GigaOpt postEco DRV Optimization
Running refinePlace -preserveRouting true -hardFence false
*** Starting refinePlace (0:14:04 mem=2453.6M) ***
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 8563 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Starting Small incrNP...
Density distribution unevenness ratio = 8.989%
Skipped incrNP (cpu=0:00:00.0, real=0:00:00.0, mem=2453.6M)
End of Small incrNP (cpu=0:00:00.0, real=0:00:00.0)
Move report: Detail placement moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM: 2453.6MB
Summary Report:
Instances move: 0 (out of 8532 movable)
Instances flipped: 0
Mean displacement: 0.00 um
Max displacement: 0.00 um
Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM: 2453.6MB
*** Finished refinePlace (0:14:05 mem=2453.6M) ***
Active setup views:
default
Dominating endpoints: 0
Dominating TNS: -0.000
Extraction called for design 'DLX' of instances=8563 and nets=9457 using extraction engine 'preRoute' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PreRoute RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
RCMode: PreRoute
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
PreRoute extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Using capacitance table file ...
Updating RC grid for preRoute extraction ...
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
PreRoute RC Extraction DONE (CPU Time: 0:00:00.4 Real Time: 0:00:00.0 MEM: 2056.070M)
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PreRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2120.61)
Total number of fetched objects 9953
End delay calculation. (MEM=2440.39 CPU=0:00:07.3 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2440.39 CPU=0:00:08.9 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:13.9 real=0:00:03.0 totSessionCpu=0:14:20 mem=2440.4M)
Reported timing to dir ./timingReports
**optDesign ... cpu = 0:02:16, real = 0:00:53, mem = 1577.4M, totSessionCpu=0:14:20 **
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.665 | 0.665 | 0.718 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
**optDesign ... cpu = 0:02:18, real = 0:00:56, mem = 1576.8M, totSessionCpu=0:14:22 **
*** Finished optDesign ***
Info: Destroy the CCOpt slew target map.
<CMD> getFillerMode -quiet
<CMD> addFiller -cell FILLCELL_X1 FILLCELL_X8 FILLCELL_X4 FILLCELL_X32 FILLCELL_X2 FILLCELL_X16 -prefix FILLER
*INFO: Adding fillers to top-module.
*INFO: Added 243 filler insts (cell FILLCELL_X32 / prefix FILLER).
*INFO: Added 502 filler insts (cell FILLCELL_X16 / prefix FILLER).
*INFO: Added 2046 filler insts (cell FILLCELL_X8 / prefix FILLER).
*INFO: Added 3560 filler insts (cell FILLCELL_X4 / prefix FILLER).
*INFO: Added 11208 filler insts (cell FILLCELL_X1 / prefix FILLER).
*INFO: Added 0 filler inst (cell FILLCELL_X2 / prefix FILLER).
*INFO: Total 17559 filler insts added - prefix FILLER (CPU: 0:00:05.2).
For 17559 new insts, *** Applied 0 GNC rules (cpu = 0:00:00.0)
<CMD> saveDesign ./physical_design/5_stage_post_filler.enc
#% Begin save design ... (date=07/19 02:46:30, mem=1497.7M)
% Begin Save ccopt configuration ... (date=07/19 02:46:30, mem=1497.7M)
% End Save ccopt configuration ... (date=07/19 02:46:30, total cpu=0:00:00.1, real=0:00:00.0, peak res=1498.1M, current mem=1498.1M)
% Begin Save netlist data ... (date=07/19 02:46:30, mem=1498.1M)
Writing Binary DB to ./physical_design/5_stage_post_filler.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:46:30, total cpu=0:00:00.1, real=0:00:00.0, peak res=1498.2M, current mem=1498.2M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/5_stage_post_filler.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:46:30, mem=1498.6M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:46:31, total cpu=0:00:00.1, real=0:00:00.0, peak res=1498.6M, current mem=1498.6M)
Saving preference file ./physical_design/5_stage_post_filler.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Saving property file ./physical_design/5_stage_post_filler.enc.dat/DLX.prop
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2152.4M) ***
Save Adaptive View Pruning View Names to Binary file
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveRoute (cpu=0:00:00.3 real=0:00:01.0 mem=2144.4M) ***
TAT_INFO: ::saveRoute REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
#Saving pin access data to file ./physical_design/5_stage_post_filler.enc.dat/DLX.apa ...
#
TAT_INFO: ::db::saveSymbolTable REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 1 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:46:33, mem=1497.3M)
% End Save power constraints data ... (date=07/19 02:46:33, total cpu=0:00:00.0, real=0:00:00.0, peak res=1497.3M, current mem=1497.3M)
high standard low
Generated self-contained design 5_stage_post_filler.enc.dat
#% End save design ... (date=07/19 02:46:51, total cpu=0:00:19.5, real=0:00:21.0, peak res=1498.6M, current mem=1497.2M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> setNanoRouteMode -quiet -routeTopRoutingLayer 6
#WARNING (NRIF-91) Option setNanoRouteMode -routeTopRoutingLayer is obsolete. It will continue to work for the current release. To ensure compatibility with future releases, use option setDesignMode -topRoutingLayer instead.
<CMD> setNanoRouteMode -quiet -routeBottomRoutingLayer default
<CMD> setNanoRouteMode -quiet -drouteEndIteration default
<CMD> setNanoRouteMode -quiet -routeWithTimingDriven false
<CMD> setNanoRouteMode -quiet -routeWithSiDriven false
<CMD> routeDesign -globalDetail
#% Begin routeDesign (date=07/19 02:46:51, mem=1497.2M)
#routeDesign: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1497.21 (MB), peak = 1866.92 (MB)
#WARNING (NRIG-96) Selected single pass global detail route "-globalDetail". Clock eco and post optimizations will not be run. See "man NRIG-96" for more details.
**INFO: User settings:
setNanoRouteMode -droutePostRouteSpreadWire 1
setNanoRouteMode -extractThirdPartyCompatible false
setNanoRouteMode -grouteExpTdStdDelay 10.1
setNanoRouteMode -grouteExpTdUseTifTimingEngineForImportDesign true
setNanoRouteMode -routeTopRoutingLayer 6
setNanoRouteMode -routeWithSiDriven false
setNanoRouteMode -routeWithTimingDriven false
setNanoRouteMode -timingEngine {}
setExtractRCMode -engine preRoute
setDelayCalMode -enable_high_fanout true
setDelayCalMode -eng_copyNetPropToNewNet true
setDelayCalMode -engine aae
setDelayCalMode -ignoreNetLoad false
setDelayCalMode -SIAware false
setSIMode -separate_delta_delay_on_data true
#**INFO: setDesignMode -flowEffort standard
#**INFO: multi-cut via swapping will not be performed after routing.
#**INFO: All auto set options tuned by routeDesign will be restored to their original settings on command completion.
Begin checking placement ... (start mem=2081.4M, init mem=2081.4M)
*info: Placed = 26122 (Fixed = 31)
*info: Unplaced = 0
Placement Density:100.00%(35466/35466)
Placement Density (including fixed std cells):100.00%(35466/35466)
Finished checkPlace (total: cpu=0:00:01.0, real=0:00:01.0; vio checks: cpu=0:00:00.8, real=0:00:01.0; mem=2081.4M)
changeUseClockNetStatus Option : -noFixedNetWires
*** Changed status on (32) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0, mem=2081.4M) ***
% Begin globalDetailRoute (date=07/19 02:46:52, mem=1498.9M)
globalDetailRoute
#Start globalDetailRoute on Sat Jul 19 02:46:52 2025
#
#WARNING (NRIG-1303) Congestion map does not match the GCELL grid, clearing map.
#num needed restored net=0
#need_extraction net=0 (total=9457)
#WARNING (NRDB-2005) SPECIAL_NET vdd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#WARNING (NRDB-2005) SPECIAL_NET gnd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#NanoRoute Version 20.11-s130_1 NR200802-2257/20_11-UB
#Using multithreading with 8 threads.
#Start routing data preparation on Sat Jul 19 02:46:53 2025
#
#Minimum voltage of a net in the design = 0.000.
#Maximum voltage of a net in the design = 1.100.
#Voltage range [0.000 - 1.100] has 9226 nets.
#Voltage range [0.000 - 0.000] has 230 nets.
#Voltage range [1.100 - 1.100] has 1 net.
#Rebuild pin access data for design.
#Initial pin access analysis.
#Detail pin access analysis.
# metal1 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.13500
# metal2 V Track-Pitch = 0.19000 Line-2-Via Pitch = 0.14000
# metal3 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.14000
# metal4 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal5 H Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal6 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal7 H Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal8 V Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal9 H Track-Pitch = 1.60000 Line-2-Via Pitch = 1.60000
# metal10 V Track-Pitch = 1.68000 Line-2-Via Pitch = 1.60000
#Monitoring time of adding inner blkg by smac
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1527.31 (MB), peak = 1866.92 (MB)
#Regenerating Ggrids automatically.
#Auto generating G-grids with size=15 tracks, using layer metal3's pitch = 0.14000.
#Using automatically generated G-grids.
#Done routing data preparation.
#cpu time = 00:00:02, elapsed time = 00:00:01, memory = 1527.50 (MB), peak = 1866.92 (MB)
#
#Finished routing data preparation on Sat Jul 19 02:46:53 2025
#
#Cpu time = 00:00:02
#Elapsed time = 00:00:01
#Increased memory = 7.14 (MB)
#Total memory = 1527.52 (MB)
#Peak memory = 1866.92 (MB)
#
#
#Start global routing on Sat Jul 19 02:46:53 2025
#
#
#Start global routing initialization on Sat Jul 19 02:46:53 2025
#
#Number of eco nets is 12
#
#Start global routing data preparation on Sat Jul 19 02:46:53 2025
#
#Start routing resource analysis on Sat Jul 19 02:46:53 2025
#
#Routing resource analysis is done on Sat Jul 19 02:46:53 2025
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# metal1 H 1412 0 8930 64.41%
# metal2 V 1049 0 8930 0.00%
# metal3 H 1412 0 8930 0.00%
# metal4 V 712 0 8930 0.00%
# metal5 H 705 0 8930 0.00%
# metal6 V 712 0 8930 0.00%
# --------------------------------------------------------------
# Total 6002 0.00% 53580 10.74%
#
# 32 nets (0.34%) with 1 preferred extra spacing.
#
#
#
#Global routing data preparation is done on Sat Jul 19 02:46:53 2025
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1531.52 (MB), peak = 1866.92 (MB)
#
#
#Global routing initialization is done on Sat Jul 19 02:46:54 2025
#
#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 1531.52 (MB), peak = 1866.92 (MB)
#
#start global routing iteration 1...
#cpu time = 00:00:09, elapsed time = 00:00:09, memory = 1544.66 (MB), peak = 1866.92 (MB)
#
#start global routing iteration 2...
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1546.13 (MB), peak = 1866.92 (MB)
#
#
#Total number of trivial nets (e.g. < 2 pins) = 647 (skipped).
#Total number of routable nets = 8810.
#Total number of nets in the design = 9457.
#
#8790 routable nets have only global wires.
#20 routable nets have only detail routed wires.
#12 global routed or unrouted (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.)
#20 detail routed (routable) nets have been constrained (e.g. have preferred extra spacing, require shielding etc.)
#
#Routed nets constraints summary:
#------------------------------------------------
# Rules Pref Extra Space Unconstrained
#------------------------------------------------
# Default 12 8778
#------------------------------------------------
# Total 12 8778
#------------------------------------------------
#
#Routing constraints summary of the whole design:
#------------------------------------------------
# Rules Pref Extra Space Unconstrained
#------------------------------------------------
# Default 32 8778
#------------------------------------------------
# Total 32 8778
#------------------------------------------------
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon
# #Gcell %Gcell
# Layer (1) OverCon
# --------------------------------
# metal1 0(0.00%) (0.00%)
# metal2 2(0.02%) (0.02%)
# metal3 0(0.00%) (0.00%)
# metal4 0(0.00%) (0.00%)
# metal5 0(0.00%) (0.00%)
# metal6 0(0.00%) (0.00%)
# --------------------------------
# Total 2(0.00%) (0.00%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 1
# Overflow after GR: 0.00% H + 0.00% V
#
#Hotspot report including placement blocked areas
[hotspot] +----------------+-------------------+-------------------+-------------------------------------+
[hotspot] | layer | max hotspot | total hotspot | hotspot bbox |
[hotspot] +----------------+-------------------+-------------------+-------------------------------------+
[hotspot] | metal1(H) | 514.00 | 597.00 | 5.59 11.20 190.40 190.40 |
[hotspot] | metal2(V) | 0.00 | 0.00 | (none) |
[hotspot] | metal3(H) | 0.00 | 0.00 | (none) |
[hotspot] | metal4(V) | 0.00 | 0.00 | (none) |
[hotspot] | metal5(H) | 0.00 | 0.00 | (none) |
[hotspot] | metal6(V) | 0.00 | 0.00 | (none) |
[hotspot] +----------------+-------------------+-------------------+-------------------------------------+
[hotspot] | worst | (metal1) 514.00 | (metal1) 597.00 | |
[hotspot] +----------------+-------------------+-------------------+-------------------------------------+
[hotspot] | all layers | 0.00 | 0.00 | |
[hotspot] +----------------+-------------------+-------------------+-------------------------------------+
Local HotSpot Analysis (3d): normalized congestion max/total hotspot area = 0.00/0.00 (area is in unit of 4 std-cell row bins)
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 125423 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 2 um.
#Total wire length on LAYER metal2 = 39778 um.
#Total wire length on LAYER metal3 = 57378 um.
#Total wire length on LAYER metal4 = 25364 um.
#Total wire length on LAYER metal5 = 2076 um.
#Total wire length on LAYER metal6 = 825 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 57237
#Up-Via Summary (total 57237):
#
#-----------------------
# metal1 31832
# metal2 21475
# metal3 3689
# metal4 197
# metal5 44
#-----------------------
# 57237
#
#Max overcon = 1 tracks.
#Total overcon = 0.00%.
#Worst layer Gcell overcon rate = 0.00%.
#
#Global routing statistics:
#Cpu time = 00:00:16
#Elapsed time = 00:00:15
#Increased memory = 13.64 (MB)
#Total memory = 1541.16 (MB)
#Peak memory = 1866.92 (MB)
#
#Finished global routing on Sat Jul 19 02:47:09 2025
#
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1540.48 (MB), peak = 1866.92 (MB)
#Start Track Assignment.
#Done with 14369 horizontal wires in 3 hboxes and 15062 vertical wires in 3 hboxes.
#Done with 3245 horizontal wires in 3 hboxes and 3609 vertical wires in 3 hboxes.
#Done with 3 horizontal wires in 3 hboxes and 3 vertical wires in 3 hboxes.
#
#Track assignment summary:
# layer (wire length) (overlap) (long ovlp) (with obs/pg/clk)
#------------------------------------------------------------------------
# metal1 2.35 100.00% 0.00% 100.00%
# metal2 39533.34 0.06% 0.00% 0.00%
# metal3 54599.22 0.03% 0.00% 0.00%
# metal4 23237.90 0.02% 0.00% 0.02%
# metal5 1686.81 0.00% 0.00% 0.00%
# metal6 830.34 0.00% 0.00% 0.00%
#------------------------------------------------------------------------
# All 119889.97 0.04% 0.00% 0.00%
#Complete Track Assignment.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 131921 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 4626 um.
#Total wire length on LAYER metal2 = 39636 um.
#Total wire length on LAYER metal3 = 59164 um.
#Total wire length on LAYER metal4 = 25573 um.
#Total wire length on LAYER metal5 = 2082 um.
#Total wire length on LAYER metal6 = 841 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 57237
#Up-Via Summary (total 57237):
#
#-----------------------
# metal1 31832
# metal2 21475
# metal3 3689
# metal4 197
# metal5 44
#-----------------------
# 57237
#
#cpu time = 00:00:06, elapsed time = 00:00:04, memory = 1540.63 (MB), peak = 1866.92 (MB)
#
#number of short segments in preferred routing layers
# metal3 Total
# 1 1
#
#Routing data preparation, pin analysis, global routing and track assignment statistics:
#Cpu time = 00:00:24
#Elapsed time = 00:00:21
#Increased memory = 20.48 (MB)
#Total memory = 1540.86 (MB)
#Peak memory = 1866.92 (MB)
#Using multithreading with 8 threads.
#
#Start Detail Routing..
#start initial detail routing ...
# number of violations = 6
#
# By Layer and Type :
# MetSpc Short Totals
# metal1 0 0 0
# metal2 1 5 6
# Totals 1 5 6
#18343 out of 26122 instances (70.2%) need to be verified(marked ipoed), dirty area = 46.9%.
# number of violations = 6
#
# By Layer and Type :
# MetSpc Short Totals
# metal1 0 0 0
# metal2 1 5 6
# Totals 1 5 6
#cpu time = 00:01:38, elapsed time = 00:00:12, memory = 1563.99 (MB), peak = 1866.92 (MB)
#start 1st optimization iteration ...
# number of violations = 3
#
# By Layer and Type :
# Short Totals
# metal1 0 0
# metal2 3 3
# Totals 3 3
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1561.32 (MB), peak = 1866.92 (MB)
#start 2nd optimization iteration ...
# number of violations = 3
#
# By Layer and Type :
# MetSpc Short Totals
# metal1 0 0 0
# metal2 2 1 3
# Totals 2 1 3
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1560.25 (MB), peak = 1866.92 (MB)
#start 3rd optimization iteration ...
# number of violations = 0
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1559.86 (MB), peak = 1866.92 (MB)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 133540 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 47797 um.
#Total wire length on LAYER metal3 = 52953 um.
#Total wire length on LAYER metal4 = 24441 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
#Total number of DRC violations = 0
#Cpu time = 00:01:40
#Elapsed time = 00:00:13
#Increased memory = 17.66 (MB)
#Total memory = 1558.52 (MB)
#Peak memory = 1866.92 (MB)
#
#Start Post Route wire spreading..
#
#Start DRC checking..
# number of violations = 0
#cpu time = 00:00:13, elapsed time = 00:00:02, memory = 1560.83 (MB), peak = 1866.92 (MB)
#CELL_VIEW DLX,init has no DRC violation.
#Total number of DRC violations = 0
#
#Start data preparation for wire spreading...
#
#Data preparation is done on Sat Jul 19 02:47:29 2025
#
#
#Start Post Route Wire Spread.
#Done with 4649 horizontal wires in 6 hboxes and 3313 vertical wires in 6 hboxes.
#Complete Post Route Wire Spread.
#
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 136336 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 48767 um.
#Total wire length on LAYER metal3 = 54386 um.
#Total wire length on LAYER metal4 = 24833 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
#
#Start DRC checking..
# number of violations = 0
#cpu time = 00:00:14, elapsed time = 00:00:02, memory = 1561.57 (MB), peak = 1866.92 (MB)
#CELL_VIEW DLX,init has no DRC violation.
#Total number of DRC violations = 0
# number of violations = 0
#cpu time = 00:00:18, elapsed time = 00:00:03, memory = 1561.57 (MB), peak = 1866.92 (MB)
#CELL_VIEW DLX,init has no DRC violation.
#Total number of DRC violations = 0
#Post Route wire spread is done.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 136336 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 48767 um.
#Total wire length on LAYER metal3 = 54386 um.
#Total wire length on LAYER metal4 = 24833 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
#detailRoute Statistics:
#Cpu time = 00:02:12
#Elapsed time = 00:00:19
#Increased memory = 19.36 (MB)
#Total memory = 1560.22 (MB)
#Peak memory = 1866.92 (MB)
#
#globalDetailRoute statistics:
#Cpu time = 00:02:38
#Elapsed time = 00:00:41
#Increased memory = -61.07 (MB)
#Total memory = 1437.88 (MB)
#Peak memory = 1866.92 (MB)
#Number of warnings = 3
#Total number of warnings = 12
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Sat Jul 19 02:47:33 2025
#
% End globalDetailRoute (date=07/19 02:47:33, total cpu=0:02:39, real=0:00:41.0, peak res=1733.5M, current mem=1399.9M)
#Default setup view is reset to default.
#Default setup view is reset to default.
#routeDesign: cpu time = 00:02:40, elapsed time = 00:00:42, memory = 1392.30 (MB), peak = 1866.92 (MB)
*** Message Summary: 0 warning(s), 0 error(s)
#% End routeDesign (date=07/19 02:47:34, total cpu=0:02:40, real=0:00:43.0, peak res=1733.5M, current mem=1392.3M)
<CMD> redirect -quiet {set honorDomain [getAnalysisMode -honorClockDomains]} > /dev/null
<CMD> timeDesign -postRoute -pathReports -drvReports -slackReports -numPaths 10 -prefix DLX_preRoute_setup -outDir ./physical_design/timingReport
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
Extraction called for design 'DLX' of instances=26122 and nets=9457 using extraction engine 'postRoute' at effort level 'low' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PostRoute (effortLevel low) RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
Process corner(s) are loaded.
Corner: standard
extractDetailRC Option : -outfile /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/DLX_10677_KnhU5U.rcdb.d -extended
RC Mode: PostRoute -effortLevel low [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Coupling Cap. Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:00.1 MEM= 2046.1M)
Extracted 10.0015% (CPU Time= 0:00:00.6 MEM= 2113.8M)
Extracted 20.002% (CPU Time= 0:00:00.8 MEM= 2113.8M)
Extracted 30.0015% (CPU Time= 0:00:00.8 MEM= 2113.8M)
Extracted 40.002% (CPU Time= 0:00:01.0 MEM= 2113.8M)
Extracted 50.0015% (CPU Time= 0:00:01.2 MEM= 2113.8M)
Extracted 60.002% (CPU Time= 0:00:01.3 MEM= 2113.8M)
Extracted 70.0015% (CPU Time= 0:00:01.4 MEM= 2113.8M)
Extracted 80.002% (CPU Time= 0:00:01.6 MEM= 2113.8M)
Extracted 90.0015% (CPU Time= 0:00:01.8 MEM= 2113.8M)
Extracted 100% (CPU Time= 0:00:02.3 MEM= 2113.8M)
Number of Extracted Resistors : 158797
Number of Extracted Ground Cap. : 167599
Number of Extracted Coupling Cap. : 0
PostRoute (effortLevel low) RC Extraction DONE (CPU Time: 0:00:03.7 Real Time: 0:00:03.0 MEM: 2089.797M)
Starting delay calculation for Setup views
AAE DB initialization (MEM=2120.82 CPU=0:00:00.0 REAL=0:00:00.0)
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2120.82)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
siFlow : Timing analysis mode is single, using late cdB files
AAE_INFO: 8 threads acquired from CTE.
Total number of fetched objects 9953
End delay calculation. (MEM=2603.66 CPU=0:00:07.3 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2453.81 CPU=0:00:09.1 REAL=0:00:03.0)
*** Done Building Timing Graph (cpu=0:00:11.7 real=0:00:03.0 totSessionCpu=0:17:45 mem=2453.8M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.668 | 0.668 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 19.66 sec
Total Real time: 11.0 sec
Total Memory Usage: 2133.335938 Mbytes
<CMD> timeDesign -postRoute -hold -pathReports -slackReports -numPaths 10 -prefix DLX_preRoute_hold -outDir ./physical_design/timingReport
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2109.43)
Total number of fetched objects 9953
End delay calculation. (MEM=2451.42 CPU=0:00:06.4 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2451.42 CPU=0:00:07.3 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:09.0 real=0:00:02.0 totSessionCpu=0:17:59 mem=2451.4M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Hold views included:
default
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.221 | 0.073 | -0.221 |
| TNS (ns):| -71.599 | 0.000 | -71.599 |
| Violating Paths:| 1199 | 0 | 1199 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 12.69 sec
Total Real time: 3.0 sec
Total Memory Usage: 2060.902344 Mbytes
<CMD> optDesign -postRoute
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 1448.3M, totSessionCpu=0:17:59 **
**INFO: User settings:
setNanoRouteMode -droutePostRouteSpreadWire 1
setNanoRouteMode -extractThirdPartyCompatible false
setNanoRouteMode -grouteExpTdStdDelay 10.1
setNanoRouteMode -grouteExpTdUseTifTimingEngineForImportDesign false
setNanoRouteMode -routeTopRoutingLayer 6
setNanoRouteMode -routeWithSiDriven false
setNanoRouteMode -routeWithTimingDriven false
setNanoRouteMode -timingEngine {}
setExtractRCMode -coupled false
setExtractRCMode -engine postRoute
setUsefulSkewMode -ecoRoute false
setUsefulSkewMode -maxAllowedDelay 1
setUsefulSkewMode -maxSkew false
setUsefulSkewMode -noBoundary false
setUsefulSkewMode -useCells {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32 CLKBUF_X1 CLKBUF_X2 CLKBUF_X3 INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32}
setDelayCalMode -enable_high_fanout true
setDelayCalMode -eng_copyNetPropToNewNet true
setDelayCalMode -engine aae
setDelayCalMode -ignoreNetLoad false
setDelayCalMode -SIAware false
setOptMode -activeSetupViews { default }
setOptMode -autoSetupViews { default}
setOptMode -autoTDGRSetupViews { default}
setOptMode -drcMargin 0
setOptMode -fixDrc true
setOptMode -preserveAllSequential false
setOptMode -setupTargetSlack 0
setSIMode -separate_delta_delay_on_data true
setPlaceMode -maxRouteLayer 6
setPlaceMode -place_design_floorplan_mode false
setPlaceMode -place_detail_check_route false
setPlaceMode -place_detail_preserve_routing true
setPlaceMode -place_detail_remove_affected_routing false
setPlaceMode -place_detail_swap_eeq_cells false
setPlaceMode -place_global_clock_gate_aware true
setPlaceMode -place_global_cong_effort auto
setPlaceMode -place_global_ignore_scan true
setPlaceMode -place_global_ignore_spare false
setPlaceMode -place_global_module_aware_spare false
setPlaceMode -place_global_place_io_pins true
setPlaceMode -place_global_reorder_scan true
setPlaceMode -powerDriven false
setPlaceMode -timingDriven true
setAnalysisMode -analysisType single
setAnalysisMode -checkType setup
setAnalysisMode -clkSrcPath true
setAnalysisMode -clockPropagation sdcControl
setAnalysisMode -skew true
setAnalysisMode -virtualIPO false
**INFO: setDesignMode -flowEffort standard -> setting 'setOptMode -allEndPoints true' for the duration of this command.
Disable merging buffers from different footprints for postRoute code for non-MSV designs
Need call spDPlaceInit before registerPrioInstLoc.
GigaOpt running with 8 threads.
**optDesign ... cpu = 0:00:03, real = 0:00:03, mem = 1476.5M, totSessionCpu=0:18:02 **
Existing Dirty Nets : 0
New Signature Flow (optDesignCheckOptions) ....
#Taking db snapshot
#Taking db snapshot ... done
Begin checking placement ... (start mem=2096.9M, init mem=2096.9M)
*info: Placed = 26122 (Fixed = 31)
*info: Unplaced = 0
Placement Density:100.00%(35466/35466)
Placement Density (including fixed std cells):100.00%(35466/35466)
Finished checkPlace (total: cpu=0:00:01.6, real=0:00:00.0; vio checks: cpu=0:00:01.4, real=0:00:00.0; mem=2096.9M)
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0
Hold Target Slack: user slack 0
Multi-VT timing optimization disabled based on library information.
** INFO : this run is activating 'postRoute' automaton
Extraction called for design 'DLX' of instances=26122 and nets=9457 using extraction engine 'postRoute' at effort level 'low' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PostRoute (effortLevel low) RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
Process corner(s) are loaded.
Corner: standard
extractDetailRC Option : -outfile /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/DLX_10677_KnhU5U.rcdb.d -maxResLength 200 -extended
RC Mode: PostRoute -effortLevel low [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Coupling Cap. Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:00.1 MEM= 2088.9M)
Extracted 10.0015% (CPU Time= 0:00:01.1 MEM= 2156.6M)
Extracted 20.002% (CPU Time= 0:00:01.4 MEM= 2156.6M)
Extracted 30.0015% (CPU Time= 0:00:01.5 MEM= 2156.6M)
Extracted 40.002% (CPU Time= 0:00:01.8 MEM= 2156.6M)
Extracted 50.0015% (CPU Time= 0:00:01.9 MEM= 2156.6M)
Extracted 60.002% (CPU Time= 0:00:02.0 MEM= 2156.6M)
Extracted 70.0015% (CPU Time= 0:00:02.2 MEM= 2156.6M)
Extracted 80.002% (CPU Time= 0:00:02.3 MEM= 2156.6M)
Extracted 90.0015% (CPU Time= 0:00:02.5 MEM= 2156.6M)
Extracted 100% (CPU Time= 0:00:03.0 MEM= 2156.6M)
Number of Extracted Resistors : 158797
Number of Extracted Ground Cap. : 167599
Number of Extracted Coupling Cap. : 0
PostRoute (effortLevel low) RC Extraction DONE (CPU Time: 0:00:04.4 Real Time: 0:00:04.0 MEM: 2124.617M)
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2130.65)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
AAE_INFO: 8 threads acquired from CTE.
Total number of fetched objects 9953
End delay calculation. (MEM=2472.63 CPU=0:00:08.0 REAL=0:00:02.0)
End delay calculation (fullDC). (MEM=2472.63 CPU=0:00:09.3 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:11.4 real=0:00:02.0 totSessionCpu=0:18:23 mem=2472.6M)
Active hold views:
default
Dominating endpoints: 0
Dominating TNS: -0.000
Done building cte hold timing graph (HoldAware) cpu=0:00:14.5 real=0:00:03.0 totSessionCpu=0:18:23 mem=2503.2M ***
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2491.65)
Total number of fetched objects 9953
End delay calculation. (MEM=2472.63 CPU=0:00:07.4 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2472.63 CPU=0:00:08.4 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:10.8 real=0:00:02.0 totSessionCpu=0:18:37 mem=2472.6M)
------------------------------------------------------------
Initial Non-SI Timing Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.668 | 0.668 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
**optDesign ... cpu = 0:00:39, real = 0:00:15, mem = 1610.8M, totSessionCpu=0:18:39 **
Info: Done creating the CCOpt slew target map.
Running CCOpt-PRO on entire clock network
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=32, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 9425 (unrouted=647, trialRouted=0, noStatus=0, routed=8778, fixed=0, [crossesIlmBoundary=0, tooFewTerms=647, (crossesIlmBoundary AND tooFewTerms=0)])
Clock tree cells fixed by user: 0 out of 31 (0%)
PRO...
Relaxing adjacent_rows_legal and cell_density for the duration of PRO. To stop this set pro_respect_cell_density_and_adjacent_row_legal to true.
Initializing clock structures...
Creating own balancer
Permitting the movement of (non-FIXED) datapath insts as required for sized/new clock tree insts
Removing CTS place status from clock tree and sinks.
Initializing legalizer
Using cell based legalization.
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
Reconstructing clock tree datastructures, skew aware...
Validating CTS configuration...
Checking module port directions...
Checking module port directions done. (took cpu=0:00:00.0 real=0:00:00.0)
Non-default CCOpt properties:
adjacent_rows_legal: true (default: false)
allow_non_fterm_identical_swaps: 0 (default: true)
cell_density is set for at least one object
cell_halo_rows: 0 (default: 1)
cell_halo_sites: 0 (default: 4)
clock_nets_detailed_routed: 1 (default: false)
force_design_routing_status: 1 (default: auto)
primary_delay_corner: std-typ (default: )
route_type is set for at least one object
target_insertion_delay is set for at least one object
target_max_trans is set for at least one object
target_skew is set for at least one object
target_skew_wire is set for at least one object
Route type trimming info:
No route type modifications were made.
**WARN: (IMPCCOPT-1184): The library has no usable balanced inverters for power domain auto-default, while balancing clock_tree clk. If this is not intended behavior, you can specify a list of lib_cells to use with the inverter_cells property.
Clock tree balancer configuration for clock_tree clk:
Non-default CCOpt properties:
cell_density: 1 (default: 0.75)
route_type (leaf): default_route_type_leaf (default: default)
route_type (trunk): default_route_type_nonleaf (default: default)
route_type (top): default_route_type_nonleaf (default: default)
For power domain auto-default:
Buffers: CLKBUF_X3 CLKBUF_X2 CLKBUF_X1
Inverters:
Clock gates (with test): CLKGATETST_X8 CLKGATETST_X4 CLKGATETST_X2 CLKGATETST_X1
Clock gates (no test): CLKGATE_X8 CLKGATE_X4 CLKGATE_X2 CLKGATE_X1
Unblocked area available for placement of any clock cells in power_domain auto-default: 35465.780um^2
Top Routing info:
Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Mask Constraint: 0; Source: route_type.
Trunk Routing info:
Route-type name: default_route_type_nonleaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: route_type.
Leaf Routing info:
Route-type name: default_route_type_leaf; Top/bottom preferred layer name: metal4/metal3;
Unshielded; Preferred extra space: 1; Mask Constraint: 0; Source: route_type.
For timing_corner std-typ:both, late and power domain auto-default:
Slew time target (leaf): 0.050ns
Slew time target (trunk): 0.050ns
Slew time target (top): 0.050ns (Note: no nets are considered top nets in this clock tree)
Buffer unit delay: 0.042ns
Buffer max distance: 383.704um
Fastest wire driving cells and distances:
Buffer : {lib_cell:CLKBUF_X3, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=383.704um, saturatedSlew=0.043ns, speed=4030.504um per ns, cellArea=3.466um^2 per 1000um}
Clock gate (with test): {lib_cell:CLKGATETST_X8, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=550.588um, saturatedSlew=0.043ns, speed=5682.023um per ns, cellArea=14.010um^2 per 1000um}
Clock gate (no test): {lib_cell:CLKGATE_X8, fastest_considered_half_corner=std-typ:both.late, optimalDrivingDistance=549.600um, saturatedSlew=0.044ns, speed=5878.075um per ns, cellArea=12.584um^2 per 1000um}
Logic Sizing Table:
----------------------------------------------------------
Cell Instance count Source Eligible library cells
----------------------------------------------------------
(empty table)
----------------------------------------------------------
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Clock tree balancer configuration for skew_group clk/coherent-synthesis:
Sources: pin clk
Total number of sinks: 1325
Delay constrained sinks: 1325
Non-leaf sinks: 0
Ignore pins: 0
Timing corner std-typ:both.late:
Skew target: 0.042ns
Primary reporting skew groups are:
skew_group clk/coherent-synthesis with 1325 clock sinks
Clock DAG stats initial state:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG library cell distribution initial state {count}:
Bufs: CLKBUF_X3: 31
Have 8 CPUs available for CTS. Selected algorithms will run multithreaded.
No ideal or dont_touch nets found in the clock tree
No dont_touch hnets found in the clock tree
Validating CTS configuration done. (took cpu=0:00:01.6 real=0:00:01.6)
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
CCOpt configuration status: all checks passed.
Reconstructing clock tree datastructures, skew aware done.
Initializing clock structures done.
PRO...
PRO active optimizations:
- DRV fixing with cell sizing
Detected clock skew data from CTS
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.8 real=0:00:00.2)
Clock DAG stats PRO initial state:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=50.411fF, leaf=456.292fF, total=506.703fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4678.620um, total=5256.730um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations PRO initial state: none
Clock DAG primary half-corner transition distribution PRO initial state:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.045ns sd=0.003ns min=0.036ns max=0.048ns {0 <= 0.030ns, 2 <= 0.040ns, 11 <= 0.045ns, 17 <= 0.048ns, 1 <= 0.050ns}
Clock DAG library cell distribution PRO initial state {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups PRO initial state:
skew_group default.clk/coherent-synthesis: unconstrained
Skew group summary PRO initial state:
skew_group clk/coherent-synthesis: insertion delay [min=0.065, max=0.085, avg=0.078, sd=0.004], skew [0.020 vs 0.042], 100% {0.065, 0.085} (wid=0.014 ws=0.012) (gid=0.075 gs=0.018)
Recomputing CTS skew targets...
Resolving skew group constraints...
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Solving LP: 1 skew groups; 2 fragments, 2 fraglets and 3 vertices; 25 variables and 66 constraints; tolerance 1
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Resolving skew group constraints done.
**WARN: (IMPCCOPT-1261): The skew target of 0.020ns for skew_group clk/coherent-synthesis is too small. For best results, it is recommended that the skew target be set no lower than 0.042ns. The skew target has been relaxed to 0.042ns. You may force the use of the tighter skew target by setting override_minimum_skew_target to true.
Type 'man IMPCCOPT-1261' for more detail.
Recomputing CTS skew targets done. (took cpu=0:00:00.2 real=0:00:00.2)
PRO Fixing DRVs...
Fixing clock tree DRVs: ...20% ...40% ...60% ...80% ...100%
CCOpt-PRO: considered: 32, tested: 32, violation detected: 0, violation ignored (due to small violation): 0, cannot run: 0, attempted: 0, unsuccessful: 0, sized: 0
PRO Statistics: Fix DRVs (cell sizing):
=======================================
Cell changes by Net Type:
-------------------------------------------------------------------------------------------------
Net Type Attempted Upsized Downsized Swapped Same Size Total Changed Not Sized
-------------------------------------------------------------------------------------------------
top 0 0 0 0 0 0
trunk 0 0 0 0 0 0
leaf 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Total 0 0 0 0 0 0
-------------------------------------------------------------------------------------------------
Upsized: 0, Downsized: 0, Sized but same area: 0, Unchanged: 0, Area change: 0.000um^2 (0.000%)
Max. move: 0.000um, Min. move: 0.000um, Avg. move: N/A
Clock DAG stats after 'PRO Fixing DRVs':
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=50.411fF, leaf=456.292fF, total=506.703fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4678.620um, total=5256.730um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations after 'PRO Fixing DRVs': none
Clock DAG primary half-corner transition distribution after 'PRO Fixing DRVs':
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.045ns sd=0.003ns min=0.036ns max=0.048ns {0 <= 0.030ns, 2 <= 0.040ns, 11 <= 0.045ns, 17 <= 0.048ns, 1 <= 0.050ns}
Clock DAG library cell distribution after 'PRO Fixing DRVs' {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups after 'PRO Fixing DRVs':
skew_group default.clk/coherent-synthesis: unconstrained
Skew group summary after 'PRO Fixing DRVs':
skew_group clk/coherent-synthesis: insertion delay [min=0.065, max=0.085, avg=0.078, sd=0.004], skew [0.020 vs 0.042], 100% {0.065, 0.085} (wid=0.014 ws=0.012) (gid=0.075 gs=0.018)
Legalizer API calls during this step: 0 succeeded with high effort: 0 succeeded with medium effort: 0 succeeded with low effort: 0 succeeded with basic effort: 0 succeeded with basic unbounded effort: 0
PRO Fixing DRVs done. (took cpu=0:00:00.1 real=0:00:00.1)
Reconnecting optimized routes...
Reconnecting optimized routes done. (took cpu=0:00:00.0 real=0:00:00.0)
Set dirty flag on 0 instances, 0 nets
Clock tree timing engine global stage delay update for std-typ:both.late...
Clock tree timing engine global stage delay update for std-typ:both.late done. (took cpu=0:00:00.8 real=0:00:00.2)
Clock DAG stats PRO final:
cell counts : b=31, i=0, icg=0, nicg=0, l=0, total=31
cell areas : b=41.230um^2, i=0.000um^2, icg=0.000um^2, nicg=0.000um^2, l=0.000um^2, total=41.230um^2
cell capacitance : b=44.056fF, i=0.000fF, icg=0.000fF, nicg=0.000fF, l=0.000fF, total=44.056fF
sink capacitance : count=1325, total=1293.592fF, avg=0.976fF, sd=0.003fF, min=0.950fF, max=0.977fF
wire capacitance : top=0.000fF, trunk=50.411fF, leaf=456.292fF, total=506.703fF
wire lengths : top=0.000um, trunk=578.110um, leaf=4678.620um, total=5256.730um
hp wire lengths : top=0.000um, trunk=0.000um, leaf=1874.495um, total=1874.495um
Clock DAG net violations PRO final: none
Clock DAG primary half-corner transition distribution PRO final:
Trunk : target=0.050ns count=1 avg=0.008ns sd=0.000ns min=0.008ns max=0.008ns {1 <= 0.030ns, 0 <= 0.040ns, 0 <= 0.045ns, 0 <= 0.048ns, 0 <= 0.050ns}
Leaf : target=0.050ns count=31 avg=0.045ns sd=0.003ns min=0.036ns max=0.048ns {0 <= 0.030ns, 2 <= 0.040ns, 11 <= 0.045ns, 17 <= 0.048ns, 1 <= 0.050ns}
Clock DAG library cell distribution PRO final {count}:
Bufs: CLKBUF_X3: 31
Primary reporting skew groups PRO final:
skew_group default.clk/coherent-synthesis: unconstrained
Skew group summary PRO final:
skew_group clk/coherent-synthesis: insertion delay [min=0.065, max=0.085, avg=0.078, sd=0.004], skew [0.020 vs 0.042], 100% {0.065, 0.085} (wid=0.014 ws=0.012) (gid=0.075 gs=0.018)
PRO done.
Restoring CTS place status for unmodified clock tree cells and sinks.
Net route status summary:
Clock: 32 (unrouted=0, trialRouted=0, noStatus=0, routed=32, fixed=0, [crossesIlmBoundary=0, tooFewTerms=0, (crossesIlmBoundary AND tooFewTerms=0)])
Non-clock: 9425 (unrouted=647, trialRouted=0, noStatus=0, routed=8778, fixed=0, [crossesIlmBoundary=0, tooFewTerms=647, (crossesIlmBoundary AND tooFewTerms=0)])
Updating delays...
Updating delays done.
PRO done. (took cpu=0:00:04.2 real=0:00:02.9)
**WARN: (IMPSP-105): 'setPlaceMode -maxRouteLayer' will become obsolete from next release. Use 'setRouteMode -earlyGlobalMaxRouteLayer N' to set maximum routing layer.Type 'man IMPSP-105' for more detail.
**INFO: Start fixing DRV (Mem = 2189.99M) ...
Begin: GigaOpt DRV Optimization
Info: 32 clock nets excluded from IPO operation.
*** DrvOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:18:44.2/0:08:07.6 (2.3), mem = 2190.0M
DRV pessimism of 2.00% is used for tran, 2.00% for cap, 2.00% for fanout, on top of margin 0.00%
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| max-tran | max-cap | max-fanout | max-length | setup | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| nets | terms| wViol | nets | terms| wViol | nets | terms| nets | terms| WNS | TNS | #Buf | #Inv | #Resize|Density| Real | Mem |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.67| 0.00| 0| 0| 0| 100.00| | |
| 0| 0| 0.00| 0| 0| 0.00| 0| 0| 0| 0| 0.67| 0.00| 0| 0| 0| 100.00| 0:00:00.0| 2492.2M|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Bottom Preferred Layer:
+---------------+------------+----------+
| Layer | CLK | Rule |
+---------------+------------+----------+
| metal3 (z=3) | 32 | default |
+---------------+------------+----------+
Via Pillar Rule:
None
*** Finish DRV Fixing (cpu=0:00:00.7 real=0:00:00.0 mem=2492.3M) ***
*** DrvOpt [finish] : cpu/real = 0:00:05.3/0:00:04.7 (1.1), totSession cpu/real = 0:18:49.5/0:08:12.3 (2.3), mem = 2284.3M
drv optimizer changes nothing and skips refinePlace
End: GigaOpt DRV Optimization
*info:
**INFO: Completed fixing DRV (CPU Time = 0:00:05, Mem = 2237.28M).
------------------------------------------------------------
Non-SI Timing Summary (cpu=0.09min real=0.07min mem=2237.3M)
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.721 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
**optDesign ... cpu = 0:00:51, real = 0:00:24, mem = 1675.4M, totSessionCpu=0:18:51 **
*** Timing Is met
*** Check timing (0:00:00.0)
*** Setup timing is met (target slack 0ns)
Running postRoute recovery in preEcoRoute mode
**optDesign ... cpu = 0:00:52, real = 0:00:24, mem = 1675.8M, totSessionCpu=0:18:51 **
Checking DRV degradation...
**INFO: Skipping DRV recovery as drv did not degrade beyond margin
Finish postRoute recovery in preEcoRoute mode (cpu=0:00:01, real=0:00:00, mem=2236.75M, totSessionCpu=0:18:52).
**optDesign ... cpu = 0:00:53, real = 0:00:24, mem = 1675.8M, totSessionCpu=0:18:52 **
Skipping post route harden opt
Default Rule : ""
Non Default Rules :
Worst Slack : 0.668 ns
Start Layer Assignment ...
WNS(0.668ns) Target(0.000ns) MaxAssign(0%) MaxCong(20%) MinLen(100um) MinCap(0.050pf) layerBucket(1)
Select 0 cadidates out of 9457.
No critical nets selected. Skipped !
Start Assign Priority Nets ...
TargetSlk(0.200ns) MaxAssign(3%) minLen(50um)
Existing Priority Nets 0 (0.0%)
Assigned Priority Nets 0 (0.0%)
Default Rule : ""
Non Default Rules :
Worst Slack : 0.668 ns
Start Layer Assignment ...
WNS(0.668ns) Target(0.000ns) MaxAssign(0%) MaxCong(20%) MinLen(100um) MinCap(0.050pf) layerBucket(1)
Select 0 cadidates out of 9457.
No critical nets selected. Skipped !
Start Assign Priority Nets ...
TargetSlk(0.200ns) MaxAssign(3%) minLen(50um)
Existing Priority Nets 0 (0.0%)
Assigned Priority Nets 0 (0.0%)
------------------------------------------------------------
Pre-ecoRoute Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.721 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
Total number of glitch violations: 0
------------------------------------------------------------
**optDesign ... cpu = 0:00:55, real = 0:00:26, mem = 1627.0M, totSessionCpu=0:18:54 **
Running refinePlace -preserveRouting true -hardFence false
*** Starting refinePlace (0:18:54 mem=2197.0M) ***
**ERROR: (IMPSP-2002): Density too high (100.0%), stopping detail placement.
Type 'man IMPSP-2002' for more detail.
**WARN: (IMPSP-5140): Global net connect rules have not been created. Added insts would have no supply connectivity, and would fail DRC.
Type 'man IMPSP-5140' for more detail.
**WARN: (IMPSP-315): Found 26122 instances insts with no PG Term connections.
Type 'man IMPSP-315' for more detail.
Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM: 2197.0MB
*** Finished refinePlace (0:18:54 mem=2197.0M) ***
**ERROR: (IMPSP-9022): Command 'refinePlace' completed with some error(s).
-routeWithEco false # bool, default=false
-routeWithEco true # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
Existing Dirty Nets : 0
New Signature Flow (saveAndSetNanoRouteOptions) ....
Reset Dirty Nets : 0
globalDetailRoute
#Start globalDetailRoute on Sat Jul 19 02:48:14 2025
#
#num needed restored net=0
#need_extraction net=0 (total=9457)
#WARNING (NRDB-2005) SPECIAL_NET vdd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#WARNING (NRDB-2005) SPECIAL_NET gnd has special wires but no definitions for instance pins or top level pins. This will cause routability problems later.
#Processed 0/0 dirty instances, 0/0 dirty terms, 0/0 dirty fterms, 0/0 dirty pgterms, 0/0 misc dirty regions(0 insts marked dirty, reset pre-exisiting dirty flag on 0 insts, 0 nets marked need extraction)
#NanoRoute Version 20.11-s130_1 NR200802-2257/20_11-UB
#Skip comparing routing design signature in db-snapshot flow
#Using multithreading with 8 threads.
#Start routing data preparation on Sat Jul 19 02:48:15 2025
#
#Minimum voltage of a net in the design = 0.000.
#Maximum voltage of a net in the design = 1.100.
#Voltage range [0.000 - 1.100] has 9226 nets.
#Voltage range [0.000 - 0.000] has 230 nets.
#Voltage range [1.100 - 1.100] has 1 net.
#Initial pin access analysis.
#Detail pin access analysis.
# metal1 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.13500
# metal2 V Track-Pitch = 0.19000 Line-2-Via Pitch = 0.14000
# metal3 H Track-Pitch = 0.14000 Line-2-Via Pitch = 0.14000
# metal4 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal5 H Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal6 V Track-Pitch = 0.28000 Line-2-Via Pitch = 0.28000
# metal7 H Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal8 V Track-Pitch = 0.84000 Line-2-Via Pitch = 0.80000
# metal9 H Track-Pitch = 1.60000 Line-2-Via Pitch = 1.60000
# metal10 V Track-Pitch = 1.68000 Line-2-Via Pitch = 1.60000
#Monitoring time of adding inner blkg by smac
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1635.59 (MB), peak = 1866.92 (MB)
#Regenerating Ggrids automatically.
#Auto generating G-grids with size=15 tracks, using layer metal3's pitch = 0.14000.
#Using automatically generated G-grids.
#Done routing data preparation.
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1636.09 (MB), peak = 1866.92 (MB)
#
#Finished routing data preparation on Sat Jul 19 02:48:15 2025
#
#Cpu time = 00:00:01
#Elapsed time = 00:00:01
#Increased memory = 4.86 (MB)
#Total memory = 1636.12 (MB)
#Peak memory = 1866.92 (MB)
#
#
#Start global routing on Sat Jul 19 02:48:15 2025
#
#
#Start global routing initialization on Sat Jul 19 02:48:15 2025
#
#WARNING (NRGR-22) Design is already detail routed.
#Routing data preparation, pin analysis, global routing and track assignment statistics:
#Cpu time = 00:00:02
#Elapsed time = 00:00:01
#Increased memory = 4.89 (MB)
#Total memory = 1636.08 (MB)
#Peak memory = 1866.92 (MB)
#Using multithreading with 8 threads.
#
#Start Detail Routing..
#start initial detail routing ...
# number of violations = 0
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1638.31 (MB), peak = 1866.92 (MB)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 136336 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 48767 um.
#Total wire length on LAYER metal3 = 54386 um.
#Total wire length on LAYER metal4 = 24833 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
#Total number of DRC violations = 0
#Cpu time = 00:00:02
#Elapsed time = 00:00:01
#Increased memory = 0.88 (MB)
#Total memory = 1636.96 (MB)
#Peak memory = 1866.92 (MB)
#
#Start Post Route wire spreading..
#
#Start data preparation for wire spreading...
#
#Data preparation is done on Sat Jul 19 02:48:17 2025
#
#
#Start Post Route Wire Spread.
#Done with 955 horizontal wires in 6 hboxes and 525 vertical wires in 6 hboxes.
#Complete Post Route Wire Spread.
#
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 136700 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 48908 um.
#Total wire length on LAYER metal3 = 54570 um.
#Total wire length on LAYER metal4 = 24872 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
# number of violations = 0
#cpu time = 00:00:03, elapsed time = 00:00:02, memory = 1638.45 (MB), peak = 1866.92 (MB)
#CELL_VIEW DLX,init has no DRC violation.
#Total number of DRC violations = 0
#Post Route wire spread is done.
#Total number of nets with non-default rule or having extra spacing = 32
#Total wire length = 136700 um.
#Total half perimeter of net bounding box = 103127 um.
#Total wire length on LAYER metal1 = 5419 um.
#Total wire length on LAYER metal2 = 48908 um.
#Total wire length on LAYER metal3 = 54570 um.
#Total wire length on LAYER metal4 = 24872 um.
#Total wire length on LAYER metal5 = 2096 um.
#Total wire length on LAYER metal6 = 834 um.
#Total wire length on LAYER metal7 = 0 um.
#Total wire length on LAYER metal8 = 0 um.
#Total wire length on LAYER metal9 = 0 um.
#Total wire length on LAYER metal10 = 0 um.
#Total number of vias = 59044
#Up-Via Summary (total 59044):
#
#-----------------------
# metal1 32730
# metal2 22135
# metal3 3944
# metal4 191
# metal5 44
#-----------------------
# 59044
#
#detailRoute Statistics:
#Cpu time = 00:00:05
#Elapsed time = 00:00:03
#Increased memory = 1.02 (MB)
#Total memory = 1637.10 (MB)
#Peak memory = 1866.92 (MB)
#Skip updating routing design signature in db-snapshot flow
#
#globalDetailRoute statistics:
#Cpu time = 00:00:10
#Elapsed time = 00:00:05
#Increased memory = 1.87 (MB)
#Total memory = 1630.75 (MB)
#Peak memory = 1866.92 (MB)
#Number of warnings = 3
#Total number of warnings = 15
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Sat Jul 19 02:48:19 2025
#
**optDesign ... cpu = 0:01:05, real = 0:00:31, mem = 1623.2M, totSessionCpu=0:19:04 **
-routeWithEco false # bool, default=false
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
New Signature Flow (restoreNanoRouteOptions) ....
Extraction called for design 'DLX' of instances=26122 and nets=9457 using extraction engine 'postRoute' at effort level 'low' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PostRoute (effortLevel low) RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
Process corner(s) are loaded.
Corner: standard
extractDetailRC Option : -outfile /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/DLX_10677_KnhU5U.rcdb.d -maxResLength 200 -extended
RC Mode: PostRoute -effortLevel low [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Coupling Cap. Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:00.1 MEM= 2200.2M)
Extracted 10.0019% (CPU Time= 0:00:00.7 MEM= 2251.9M)
Extracted 20.0019% (CPU Time= 0:00:00.9 MEM= 2251.9M)
Extracted 30.0019% (CPU Time= 0:00:01.0 MEM= 2251.9M)
Extracted 40.0019% (CPU Time= 0:00:01.2 MEM= 2251.9M)
Extracted 50.0019% (CPU Time= 0:00:01.4 MEM= 2251.9M)
Extracted 60.0019% (CPU Time= 0:00:01.5 MEM= 2251.9M)
Extracted 70.0019% (CPU Time= 0:00:01.6 MEM= 2251.9M)
Extracted 80.0019% (CPU Time= 0:00:01.8 MEM= 2251.9M)
Extracted 90.0019% (CPU Time= 0:00:02.0 MEM= 2251.9M)
Extracted 100% (CPU Time= 0:00:02.5 MEM= 2251.9M)
Number of Extracted Resistors : 161552
Number of Extracted Ground Cap. : 170354
Number of Extracted Coupling Cap. : 0
PostRoute (effortLevel low) RC Extraction DONE (CPU Time: 0:00:03.9 Real Time: 0:00:04.0 MEM: 2232.883M)
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2221.37)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
AAE_INFO: 8 threads acquired from CTE.
Total number of fetched objects 9953
End delay calculation. (MEM=2542.27 CPU=0:00:07.4 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2542.27 CPU=0:00:08.5 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:13.3 real=0:00:03.0 totSessionCpu=0:19:22 mem=2542.3M)
------------------------------------------------------------
Post-ecoRoute Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
Total number of glitch violations: 0
------------------------------------------------------------
**optDesign ... cpu = 0:01:24, real = 0:00:39, mem = 1646.8M, totSessionCpu=0:19:23 **
Executing marking Critical Nets1
Footprint XOR2_X1 has at least 2 pins...
Footprint XNOR2_X1 has at least 3 pins...
Footprint TLAT_X1 has at least 4 pins...
Footprint SDFF_X1 has at least 5 pins...
*** Number of Vt Cells Partition = 1
Reported timing to dir ./timingReports
**optDesign ... cpu = 0:01:24, real = 0:00:39, mem = 1646.9M, totSessionCpu=0:19:23 **
------------------------------------------------------------
optDesign Final Non-SI Timing Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
**optDesign ... cpu = 0:01:26, real = 0:00:42, mem = 1647.3M, totSessionCpu=0:19:25 **
*** Finished optDesign ***
Info: Destroy the CCOpt slew target map.
<CMD> optDesign -postRoute -hold
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 1637.0M, totSessionCpu=0:19:25 **
**INFO: User settings:
setNanoRouteMode -drouteAntennaFactor 1
setNanoRouteMode -droutePostRouteSpreadWire 1
setNanoRouteMode -drouteStartIteration 0
setNanoRouteMode -extractThirdPartyCompatible false
setNanoRouteMode -grouteExpTdStdDelay 10.1
setNanoRouteMode -grouteExpTdUseTifTimingEngineForImportDesign false
setNanoRouteMode -routeTopRoutingLayer 6
setNanoRouteMode -routeWithSiDriven false
setNanoRouteMode -routeWithTimingDriven false
setNanoRouteMode -timingEngine {}
setExtractRCMode -coupled false
setExtractRCMode -engine postRoute
setUsefulSkewMode -ecoRoute false
setUsefulSkewMode -maxAllowedDelay 1
setUsefulSkewMode -maxSkew false
setUsefulSkewMode -noBoundary false
setUsefulSkewMode -useCells {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32 CLKBUF_X1 CLKBUF_X2 CLKBUF_X3 INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32}
setDelayCalMode -enable_high_fanout true
setDelayCalMode -eng_copyNetPropToNewNet true
setDelayCalMode -engine aae
setDelayCalMode -ignoreNetLoad false
setDelayCalMode -SIAware false
setOptMode -activeHoldViews { default }
setOptMode -activeSetupViews { default }
setOptMode -autoHoldViews { default}
setOptMode -autoSetupViews { default}
setOptMode -autoTDGRSetupViews { default}
setOptMode -autoViewHoldTargetSlack 0
setOptMode -drcMargin 0
setOptMode -fixDrc true
setOptMode -preserveAllSequential false
setOptMode -setupTargetSlack 0
setSIMode -separate_delta_delay_on_data true
setSIMode -si_reselection slack
setPlaceMode -maxRouteLayer 6
setPlaceMode -place_design_floorplan_mode false
setPlaceMode -place_detail_check_route false
setPlaceMode -place_detail_preserve_routing true
setPlaceMode -place_detail_remove_affected_routing false
setPlaceMode -place_detail_swap_eeq_cells false
setPlaceMode -place_global_clock_gate_aware true
setPlaceMode -place_global_cong_effort auto
setPlaceMode -place_global_ignore_scan true
setPlaceMode -place_global_ignore_spare false
setPlaceMode -place_global_module_aware_spare false
setPlaceMode -place_global_place_io_pins true
setPlaceMode -place_global_reorder_scan true
setPlaceMode -powerDriven false
setPlaceMode -timingDriven true
setAnalysisMode -analysisType single
setAnalysisMode -checkType setup
setAnalysisMode -clkSrcPath true
setAnalysisMode -clockPropagation sdcControl
setAnalysisMode -skew true
setAnalysisMode -virtualIPO false
**INFO: setDesignMode -flowEffort standard -> setting 'setOptMode -allEndPoints true' for the duration of this command.
Disable merging buffers from different footprints for postRoute code for non-MSV designs
GigaOpt running with 8 threads.
Need call spDPlaceInit before registerPrioInstLoc.
**optDesign ... cpu = 0:00:02, real = 0:00:02, mem = 1645.4M, totSessionCpu=0:19:27 **
Existing Dirty Nets : 0
New Signature Flow (optDesignCheckOptions) ....
#Taking db snapshot
#Taking db snapshot ... done
Begin checking placement ... (start mem=2209.7M, init mem=2209.7M)
*info: Placed = 26122 (Fixed = 31)
*info: Unplaced = 0
Placement Density:100.00%(35466/35466)
Placement Density (including fixed std cells):100.00%(35466/35466)
Finished checkPlace (total: cpu=0:00:01.0, real=0:00:00.0; vio checks: cpu=0:00:01.0, real=0:00:00.0; mem=2209.7M)
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0
Hold Target Slack: user slack 0
** INFO : this run is activating 'postRoute' automaton
Extraction called for design 'DLX' of instances=26122 and nets=9457 using extraction engine 'postRoute' at effort level 'low' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PostRoute (effortLevel low) RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
Process corner(s) are loaded.
Corner: standard
extractDetailRC Option : -outfile /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/DLX_10677_KnhU5U.rcdb.d -maxResLength 200 -extended
RC Mode: PostRoute -effortLevel low [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Coupling Cap. Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:00.1 MEM= 2201.7M)
Extracted 10.0019% (CPU Time= 0:00:00.7 MEM= 2269.4M)
Extracted 20.0019% (CPU Time= 0:00:00.9 MEM= 2269.4M)
Extracted 30.0019% (CPU Time= 0:00:01.0 MEM= 2269.4M)
Extracted 40.0019% (CPU Time= 0:00:01.1 MEM= 2269.4M)
Extracted 50.0019% (CPU Time= 0:00:01.3 MEM= 2269.4M)
Extracted 60.0019% (CPU Time= 0:00:01.4 MEM= 2269.4M)
Extracted 70.0019% (CPU Time= 0:00:01.5 MEM= 2269.4M)
Extracted 80.0019% (CPU Time= 0:00:01.7 MEM= 2269.4M)
Extracted 90.0019% (CPU Time= 0:00:01.9 MEM= 2269.4M)
Extracted 100% (CPU Time= 0:00:02.4 MEM= 2269.4M)
Number of Extracted Resistors : 161552
Number of Extracted Ground Cap. : 170354
Number of Extracted Coupling Cap. : 0
PostRoute (effortLevel low) RC Extraction DONE (CPU Time: 0:00:03.9 Real Time: 0:00:04.0 MEM: 2237.406M)
**ERROR: (IMPOPT-310): Design density (100.00%) exceeds/equals limit (95.00%).
**ERROR: (IMPOPT-310): Design density (100.00%) exceeds/equals limit (95.00%).
GigaOpt Hold Optimizer is used
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Starting initialization (fixHold) cpu=0:00:00.0 real=0:00:00.0 totSessionCpu=0:19:34 mem=2227.9M ***
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2225.89)
Total number of fetched objects 9953
End delay calculation. (MEM=2548.8 CPU=0:00:07.5 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2548.8 CPU=0:00:08.3 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:10.3 real=0:00:03.0 totSessionCpu=0:19:49 mem=2548.8M)
Done building cte hold timing graph (fixHold) cpu=0:00:15.8 real=0:00:04.0 totSessionCpu=0:19:49 mem=2548.8M ***
Done building hold timer [4163 node(s), 5504 edge(s), 1 view(s)] (fixHold) cpu=0:00:17.1 real=0:00:04.0 totSessionCpu=0:19:51 mem=2579.3M ***
Starting delay calculation for Setup views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2567.81)
Total number of fetched objects 9953
End delay calculation. (MEM=2544.8 CPU=0:00:06.9 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2544.8 CPU=0:00:07.8 REAL=0:00:02.0)
*** Done Building Timing Graph (cpu=0:00:10.3 real=0:00:02.0 totSessionCpu=0:20:04 mem=2544.8M)
Done building cte setup timing graph (fixHold) cpu=0:00:30.2 real=0:00:07.0 totSessionCpu=0:20:04 mem=2544.8M ***
*Info: minBufDelay = 21.9 ps, libStdDelay = 10.1 ps, minBufSize = 3192000 (3.0)
*Info: worst delay setup view: default
------------------------------------------------------------
Hold Opt Initial Summary
------------------------------------------------------------
Setup views included:
default
Hold views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.222 | 0.073 | -0.222 |
| TNS (ns):| -71.685 | 0.000 | -71.685 |
| Violating Paths:| 1198 | 0 | 1198 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
Total number of glitch violations: 0
------------------------------------------------------------
**optDesign ... cpu = 0:00:41, real = 0:00:16, mem = 1701.5M, totSessionCpu=0:20:06 **
*** HoldOpt [begin] : cpu/real = 0:00:00.0/0:00:00.0 (0.0), totSession cpu/real = 0:20:06.2/0:08:46.6 (2.3), mem = 2235.3M
*info: Run optDesign holdfix with 8 threads.
Info: 32 clock nets excluded from IPO operation.
Info: Done creating the CCOpt slew target map.
*** Starting Core Fixing (fixHold) cpu=0:00:33.5 real=0:00:10.0 totSessionCpu=0:20:07 mem=2546.4M density=100.000% ***
Phase I ......
Executing transform: ECO Safe Resize
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem |
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
**Info: Stopping hold fixing due to density exceeding max design density 95.000%
| 0| -0.222| -71.68| 1194| 0| 0( 0)| 100.00%| 0:00:00.0| 2576.9M|
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
Executing transform: AddBuffer + LegalResize
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
|Iter| WNS | TNS | #VP | #Buffer | #Resize(F/F) | Density | Real | Mem |
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
**Info: Stopping hold fixing due to density exceeding max design density 95.000%
| 0| -0.222| -71.68| 1194| 0| 0( 0)| 100.00%| 0:00:00.0| 2576.9M|
+----+--------+---------+--------+-----------+----------------+----------+------------+---------+
=======================================================================
Reasons for remaining hold violations
=======================================================================
*info: Total 32 net(s) have violated hold timing slacks.
Buffering failure reasons
------------------------------------------------
Resizing failure reasons
------------------------------------------------
*** Finished Core Fixing (fixHold) cpu=0:00:34.7 real=0:00:10.0 totSessionCpu=0:20:08 mem=2576.9M density=100.000% ***
*** Finish Post Route Hold Fixing (cpu=0:00:34.7 real=0:00:10.0 totSessionCpu=0:20:08 mem=2576.9M density=100.000%) ***
*** HoldOpt [finish] : cpu/real = 0:00:02.0/0:00:01.5 (1.3), totSession cpu/real = 0:20:08.2/0:08:48.1 (2.3), mem = 2367.4M
**INFO: total 0 insts, 0 nets marked don't touch
**INFO: total 0 insts, 0 nets marked don't touch DB property
**INFO: total 0 insts, 0 nets unmarked don't touch
Reported timing to dir ./timingReports
**optDesign ... cpu = 0:00:43, real = 0:00:17, mem = 1752.9M, totSessionCpu=0:20:08 **
Running 'saveTimingGraph -compress -file /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/opt_timing_graph_a76wZG/timingGraph.tgz -dir /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/opt_timing_graph_a76wZG -prefix timingGraph'
Done saveTimingGraph
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2551.1)
Total number of fetched objects 9953
End delay calculation. (MEM=2623.99 CPU=0:00:06.3 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2623.99 CPU=0:00:07.2 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:10.0 real=0:00:02.0 totSessionCpu=0:20:22 mem=2624.0M)
Running 'restoreTimingGraph -file /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/opt_timing_graph_a76wZG/timingGraph.tgz -dir /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/opt_timing_graph_a76wZG -prefix timingGraph'
Done restoreTimingGraph
------------------------------------------------------------
optDesign Final Non-SI Timing Summary
------------------------------------------------------------
Setup views included:
default
Hold views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.222 | 0.073 | -0.222 |
| TNS (ns):| -71.685 | 0.000 | -71.685 |
| Violating Paths:| 1198 | 0 | 1198 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
**optDesign ... cpu = 0:01:04, real = 0:00:28, mem = 1745.6M, totSessionCpu=0:20:29 **
*** Finished optDesign ***
Info: Destroy the CCOpt slew target map.
<CMD> saveDesign ./physical_design/5_stage_postRoute.enc
The in-memory database contained RC information but was not saved. To save
the RC information, use saveDesign's -rc option. Note: Saving RC information can be quite large,
so it should only be saved when it is really desired.
#% Begin save design ... (date=07/19 02:48:58, mem=1690.1M)
% Begin Save ccopt configuration ... (date=07/19 02:48:58, mem=1690.1M)
% End Save ccopt configuration ... (date=07/19 02:48:58, total cpu=0:00:00.1, real=0:00:00.0, peak res=1690.1M, current mem=1690.1M)
% Begin Save netlist data ... (date=07/19 02:48:58, mem=1690.1M)
Writing Binary DB to ./physical_design/5_stage_postRoute.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:48:58, total cpu=0:00:00.1, real=0:00:00.0, peak res=1691.3M, current mem=1691.3M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/5_stage_postRoute.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:48:58, mem=1691.9M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:48:58, total cpu=0:00:00.1, real=0:00:00.0, peak res=1691.9M, current mem=1691.9M)
Saving preference file ./physical_design/5_stage_postRoute.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Saving property file ./physical_design/5_stage_postRoute.enc.dat/DLX.prop
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2314.4M) ***
Save Adaptive View Pruning View Names to Binary file
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveRoute (cpu=0:00:00.3 real=0:00:00.0 mem=2306.4M) ***
TAT_INFO: ::saveRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
#Saving pin access data to file ./physical_design/5_stage_postRoute.enc.dat/DLX.apa ...
#
TAT_INFO: ::db::saveSymbolTable REAL = 1 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 1 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:49:00, mem=1692.2M)
% End Save power constraints data ... (date=07/19 02:49:00, total cpu=0:00:00.0, real=0:00:00.0, peak res=1692.2M, current mem=1692.2M)
high standard low
Generated self-contained design 5_stage_postRoute.enc.dat
#% End save design ... (date=07/19 02:49:13, total cpu=0:00:13.7, real=0:00:15.0, peak res=1693.3M, current mem=1693.3M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> win
Cannot display window in tcl mode
<CMD> redirect -quiet {set honorDomain [getAnalysisMode -honorClockDomains]} > /dev/null
<CMD> timeDesign -postRoute -pathReports -drvReports -slackReports -numPaths 10 -prefix DLX_postRoute_setup -outDir ./physical_design/timingReport
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Setup views included:
default
+--------------------+---------+---------+---------+
| Setup mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| 0.669 | 0.669 | 0.720 |
| TNS (ns):| 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 5.55 sec
Total Real time: 5.0 sec
Total Memory Usage: 2255.382812 Mbytes
<CMD> timeDesign -postRoute -hold -pathReports -slackReports -numPaths 10 -prefix DLX_postRoute_hold -outDir ./physical_design/timingReport
**WARN: (IMPOPT-7139): 'setExtractRCMode -coupled false' has been implicitly activated since current delay calulation is under SIAware false mode.
Starting delay calculation for Hold views
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2231.99)
Total number of fetched objects 9953
End delay calculation. (MEM=2569.98 CPU=0:00:07.4 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2569.98 CPU=0:00:08.2 REAL=0:00:01.0)
*** Done Building Timing Graph (cpu=0:00:10.0 real=0:00:02.0 totSessionCpu=0:21:01 mem=2570.0M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
Hold views included:
default
+--------------------+---------+---------+---------+
| Hold mode | all | reg2reg | default |
+--------------------+---------+---------+---------+
| WNS (ns):| -0.222 | 0.073 | -0.222 |
| TNS (ns):| -71.685 | 0.000 | -71.685 |
| Violating Paths:| 1198 | 0 | 1198 |
| All Paths:| 1612 | 295 | 1322 |
+--------------------+---------+---------+---------+
Density: 56.781%
(100.000% with Fillers)
------------------------------------------------------------
Reported timing to dir ./physical_design/timingReport
Total CPU time: 13.59 sec
Total Real time: 3.0 sec
Total Memory Usage: 2206.464844 Mbytes
<CMD> getAnalysisMode -checkType
-checkType setup # enums={setup hold}, default=setup, user setting
<CMD> report_timing -machine_readable -max_paths 10000 -max_slack 0.75 -path_exceptions all -late > ./physical_design/top.mtarpt
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2253.73)
Total number of fetched objects 9953
End delay calculation. (MEM=2602.64 CPU=0:00:06.9 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2602.64 CPU=0:00:07.8 REAL=0:00:01.0)
<CMD> load_timing_debug_report -name default_report ./physical_design/top.mtarpt
Parsing file ./physical_design/top.mtarpt...
<CMD> get_power_analysis_mode -leakage_power_view -quiet
<CMD> get_power_analysis_mode -analysis_view -quiet
<CMD> get_power_analysis_mode -state_dependent_leakage -quiet
<CMD> get_power_analysis_mode -dynamic_power_view -quiet
<CMD> get_power_analysis_mode -analysis_view -quiet
<CMD> extractRC
Extraction called for design 'DLX' of instances=26122 and nets=9457 using extraction engine 'postRoute' at effort level 'low' .
**WARN: (IMPEXT-3530): The process node is not set. Use the command setDesignMode -process <process node> prior to extraction for maximum accuracy and optimal automatic threshold setting.
Type 'man IMPEXT-3530' for more detail.
PostRoute (effortLevel low) RC Extraction called for design DLX.
RC Extraction called in multi-corner(1) mode.
Process corner(s) are loaded.
Corner: standard
extractDetailRC Option : -outfile /tmp/innovus_temp_10677_localhost.localdomain_ms25.2_8wvlOU/DLX_10677_KnhU5U.rcdb.d -maxResLength 200 -extended
RC Mode: PostRoute -effortLevel low [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0
Capacitance Scaling Factor : 1.00000
Coupling Cap. Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res. Scaling Factor : 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:00.1 MEM= 2289.6M)
Extracted 10.0019% (CPU Time= 0:00:01.1 MEM= 2365.3M)
Extracted 20.0019% (CPU Time= 0:00:01.3 MEM= 2365.3M)
Extracted 30.0019% (CPU Time= 0:00:01.3 MEM= 2365.3M)
Extracted 40.0019% (CPU Time= 0:00:01.5 MEM= 2365.3M)
Extracted 50.0019% (CPU Time= 0:00:01.6 MEM= 2365.3M)
Extracted 60.0019% (CPU Time= 0:00:01.7 MEM= 2365.3M)
Extracted 70.0019% (CPU Time= 0:00:01.9 MEM= 2365.3M)
Extracted 80.0019% (CPU Time= 0:00:02.0 MEM= 2365.3M)
Extracted 90.0019% (CPU Time= 0:00:02.2 MEM= 2365.3M)
Extracted 100% (CPU Time= 0:00:02.7 MEM= 2365.3M)
Number of Extracted Resistors : 161552
Number of Extracted Ground Cap. : 170354
Number of Extracted Coupling Cap. : 0
PostRoute (effortLevel low) RC Extraction DONE (CPU Time: 0:00:04.5 Real Time: 0:00:04.0 MEM: 2349.328M)
<CMD> rcOut -spef ./physical_design/DLX.spef
RC Out has the following PVT Info:
RC-typical
Dumping Spef file.....
Printing D_NET...
RC Out from RCDB Completed (CPU Time= 0:00:03.9 MEM= 2339.8M)
<CMD> verifyConnectivity -type all -error 1000 -warning 50
VERIFY_CONNECTIVITY use new engine.
******** Start: VERIFY CONNECTIVITY ********
Start Time: Sat Jul 19 02:49:30 2025
Design Name: DLX
Database Units: 2000
Design Boundary: (0.0000, 0.0000) (199.3100, 197.6800)
Error Limit = 1000; Warning Limit = 50
Check all nets
Use 8 pthreads
Begin Summary
Found no problems or warnings.
End Summary
End Time: Sat Jul 19 02:49:31 2025
Time Elapsed: 0:00:01.0
******** End: VERIFY CONNECTIVITY ********
Verification Complete : 0 Viols. 0 Wrngs.
(CPU Time: 0:00:01.0 MEM: 0.000M)
<CMD> report_power > ./physical_design/power_report.txt
Power Net Detected:
Voltage Name
0V gnd
1.1V vdd
Using Power View: default.
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in Single mode...
Start delay calculation (fullDC) (8 T). (MEM=2337.81)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
AAE_INFO: 8 threads acquired from CTE.
Total number of fetched objects 9953
End delay calculation. (MEM=2647.18 CPU=0:00:07.3 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2647.18 CPU=0:00:08.4 REAL=0:00:02.0)
Begin Power Analysis
0V gnd
1.1V vdd
Warning:
There are 2 power/gnd nets that are not connected
gnd vdd ...
Use 'globalNetConnect' to define rail connections.
[PowermeterNetlistLib::InfoMergingRails]
** WARN: (VOLTUS_POWR-2035): There are 2 power/gnd nets that are not connected
gnd vdd ...
Use 'globalNetConnect' to define rail connections.
Begin Processing Timing Library for Power Calculation
Begin Processing Timing Library for Power Calculation
Begin Processing Power Net/Grid for Power Calculation
Ended Processing Power Net/Grid for Power Calculation: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=1846.10MB/4015.98MB/1846.12MB)
Begin Processing Timing Window Data for Power Calculation
clk(1000MHz) Ended Processing Timing Window Data for Power Calculation: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=1846.22MB/4015.98MB/1846.22MB)
Begin Processing User Attributes
Ended Processing User Attributes: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=1846.26MB/4015.98MB/1846.26MB)
Begin Processing Signal Activity
Starting Levelizing
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT)
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 10%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 20%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 30%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 40%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 50%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 60%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 70%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 80%
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 90%
Finished Levelizing
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT)
Starting Activity Propagation
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT)
** INFO: (VOLTUS_POWR-1356): No default input activity has been set. Defaulting to 0.2.
Use 'set_default_switching_activity -input_activity' command to change the default activity value.
2025-Jul-19 02:49:34 (2025-Jul-19 00:49:34 GMT): 10%
Finished Activity Propagation
2025-Jul-19 02:49:35 (2025-Jul-19 00:49:35 GMT)
Ended Processing Signal Activity: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=1846.54MB/4015.98MB/1846.54MB)
Begin Power Computation
----------------------------------------------------------
# of cell(s) missing both power/leakage table: 0
# of cell(s) missing power table: 0
# of cell(s) missing leakage table: 0
# of MSMV cell(s) missing power_level: 0
----------------------------------------------------------
Starting Calculating power
2025-Jul-19 02:49:35 (2025-Jul-19 00:49:35 GMT)
Cannot locate supply power rail for net
'datapath_inst/execute_inst/FE_RN_11_0' of instance
datapath_inst/execute_inst/FE_RC_256_0
Cannot locate supply power rail for net
'datapath_inst/execute_inst/FE_RN_10_0' of instance
datapath_inst/execute_inst/FE_RC_249_0
Cannot locate supply power rail for net
'datapath_inst/execute_inst/FE_RN_9_0' of instance
datapath_inst/execute_inst/FE_RC_242_0
Cannot locate supply power rail for net
'datapath_inst/execute_inst/FE_RN_8_0' of instance
datapath_inst/execute_inst/FE_RC_234_0
Cannot locate supply power rail for net 'CU_inst/FE_RN_7_0' of instance
CU_inst/FE_RC_229_0
only first five unconnected nets are listed...
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 10%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 20%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 30%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 40%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 50%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 60%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 70%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 80%
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT): 90%
Finished Calculating power
2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT)
Ended Power Computation: (cpu=0:00:02, real=0:00:01, mem(process/total/peak)=2110.47MB/4096.01MB/2110.47MB)
Begin Processing User Attributes
Ended Processing User Attributes: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=2110.47MB/4096.01MB/2110.55MB)
Ended Power Analysis: (cpu=0:00:03, real=0:00:02, mem(process/total/peak)=2110.55MB/4096.01MB/2110.55MB)
Begin Boundary Leakage Calculation
Ended Boundary Leakage Calculation: (cpu=0:00:00, real=0:00:00,
mem(process/total/peak)=2110.55MB/4096.01MB/2110.56MB)
Begin Static Power Report Generation
*----------------------------------------------------------------------------------------
* Innovus 20.11-s130_1 (64bit) 08/05/2020 15:53 (Linux 2.6.32-431.11.2.el6.x86_64)
*
*
* Date & Time: 2025-Jul-19 02:49:36 (2025-Jul-19 00:49:36 GMT)
*
*----------------------------------------------------------------------------------------
*
* Design: DLX
*
* Liberty Libraries used:
* default: /eda/dk/nangate45/liberty/NangateOpenCellLibrary_typical_ecsm_nowlm.lib
*
* Parasitic Files used:
*
* Power Units = 1mW
*
* Time Units = 1e-09 secs
*
* report_power
*
-----------------------------------------------------------------------------------------
*
Total Power
-----------------------------------------------------------------------------------------
Total Internal Power: 12.72982578 67.6549%
Total Switching Power: 5.73385220 30.4736%
Total Leakage Power: 0.35214408 1.8715%
Total Power: 18.81582207
-----------------------------------------------------------------------------------------
Group Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
Sequential 11.02 1.116 0.2178 12.35 65.66
Macro 0 0 0 0 0
IO 0 0 0 0 0
Combinational 1.384 2.501 0.1334 4.018 21.35
Clock (Combinational) 0.3263 2.117 0.0009473 2.444 12.99
Clock (Sequential) 0 0 0 0 0
-----------------------------------------------------------------------------------------
Total 12.73 5.734 0.3521 18.82 100
-----------------------------------------------------------------------------------------
Rail Voltage Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
Default 1.1 12.73 5.734 0.3521 18.82 100
Clock Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
clk 0.3263 2.117 0.0009473 2.444 12.99
-----------------------------------------------------------------------------------------
Total 0.3263 2.117 0.0009473 2.444 12.99
-----------------------------------------------------------------------------------------
Clock: clk
Clock Period: 0.001000 usec
Clock Toggle Rate: 2000.0000 Mhz
Clock Static Probability: 0.5000
-----------------------------------------------------------------------------------------
* Power Distribution Summary:
* Highest Average Power: datapath_inst/decode_inst/decode_RF/CTS_ccl_a_buf_00124 (CLKBUF_X3): 0.08457
* Highest Leakage Power: datapath_inst/execute_inst/U35 (OAI221_X2): 0.000116
* Total Cap: 4.60821e-11 F
* Total instances in design: 8563
* Total instances in design with no power: 0
* Total instances in design with no activty: 0
* Total Fillers and Decap: 0
-----------------------------------------------------------------------------------------
Ended Static Power Report Generation: (cpu=0:00:00, real=0:00:00,
mem(process/total/peak)=2111.83MB/4096.01MB/2111.96MB)
<CMD> reportGateCount -level 5 -limit 100 -outfile ./physical_design/DLX.gateCount
Gate area 0.7980 um^2
[0] DLX Gates=25235 Cells=8563 Area=20137.8 um^2
[1] CU_inst Gates=143 Cells=44 Area=114.1 um^2
[1] datapath_inst Gates=25089 Cells=8517 Area=20021.0 um^2
[2] datapath_inst/fetch_inst Gates=508 Cells=160 Area=405.9 um^2
[2] datapath_inst/decode_inst Gates=14700 Cells=4486 Area=11730.9 um^2
[3] datapath_inst/decode_inst/decode_RF Gates=13278 Cells=3965 Area=10596.1 um^2
[3] datapath_inst/decode_inst/add_div_161 Gates=105 Cells=63 Area=83.8 um^2
[2] datapath_inst/execute_inst Gates=2313 Cells=1248 Area=1846.0 um^2
[3] datapath_inst/execute_inst/r105 Gates=236 Cells=65 Area=188.3 um^2
[3] datapath_inst/execute_inst/r99 Gates=190 Cells=162 Area=151.9 um^2
[3] datapath_inst/execute_inst/srl_123 Gates=321 Cells=217 Area=256.2 um^2
[3] datapath_inst/execute_inst/sll_121 Gates=414 Cells=224 Area=330.6 um^2
[2] datapath_inst/write_mem_rf_inst Gates=7487 Cells=2573 Area=5975.2 um^2
[3] datapath_inst/write_mem_rf_inst/DRAM_inst Gates=7147 Cells=2464 Area=5703.6 um^2
<CMD> saveNetlist ./physical_design/DLX.v
Writing Netlist "./physical_design/DLX.v" ...
<CMD> all_hold_analysis_views
<CMD> all_setup_analysis_views
<CMD> write_sdf -ideal_clock_network ./physical_design/DLX.sdf
**WARN: (SDF-808): The software is currently operating in a high performance mode which optimizes the handling of multiple timing arcs between input and output pin pairs. With the current settings, the SDF file generated will contain the same delay information for all of these arcs. To have the SDF recalculated with explicit pin pair data, you should use the option '-recompute_delay_calc'. This setting is recommended for generating SDF for functional simulation applications.
#################################################################################
# Design Stage: PostRoute
# Design Name: DLX
# Design Mode: 90nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Start delay calculation (fullDC) (8 T). (MEM=2659.7)
Total number of fetched objects 9953
End delay calculation. (MEM=2949.12 CPU=0:00:10.8 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=2949.12 CPU=0:00:11.9 REAL=0:00:01.0)
<CMD> saveDesign ./physical_design/6_stage_afterAll.enc
The in-memory database contained RC information but was not saved. To save
the RC information, use saveDesign's -rc option. Note: Saving RC information can be quite large,
so it should only be saved when it is really desired.
#% Begin save design ... (date=07/19 02:49:40, mem=2045.6M)
% Begin Save ccopt configuration ... (date=07/19 02:49:40, mem=2045.6M)
% End Save ccopt configuration ... (date=07/19 02:49:41, total cpu=0:00:00.1, real=0:00:01.0, peak res=2045.9M, current mem=2045.9M)
% Begin Save netlist data ... (date=07/19 02:49:41, mem=2045.9M)
Writing Binary DB to ./physical_design/6_stage_afterAll.enc.dat/vbin/DLX.v.bin in multi-threaded mode...
% End Save netlist data ... (date=07/19 02:49:41, total cpu=0:00:00.2, real=0:00:00.0, peak res=2048.5M, current mem=2048.5M)
Saving symbol-table file in separate thread ...
Saving congestion map file in separate thread ...
Saving congestion map file ./physical_design/6_stage_afterAll.enc.dat/DLX.route.congmap.gz ...
% Begin Save AAE data ... (date=07/19 02:49:41, mem=2048.9M)
Saving AAE Data ...
% End Save AAE data ... (date=07/19 02:49:41, total cpu=0:00:00.1, real=0:00:00.0, peak res=2048.9M, current mem=2048.9M)
Saving preference file ./physical_design/6_stage_afterAll.enc.dat/gui.pref.tcl ...
Saving mode setting ...
Saving global file ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving special route data file in separate thread ...
Saving PG Conn data in separate thread ...
Saving placement file in separate thread ...
Saving route file in separate thread ...
Saving property file in separate thread ...
** Saving stdCellPlacement_binary (version# 2) ...
Saving property file ./physical_design/6_stage_afterAll.enc.dat/DLX.prop
*** Completed saveProperty (cpu=0:00:00.0 real=0:00:00.0 mem=2699.5M) ***
Save Adaptive View Pruning View Names to Binary file
TAT_INFO: ::saveSpecialRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: savePGConnFile REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::savePlace REAL = 0 : CPU = 0 : MEM = 0.
*** Completed saveRoute (cpu=0:00:00.3 real=0:00:00.0 mem=2691.5M) ***
TAT_INFO: ::saveRoute REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::db::saveAnnotationAndProp REAL = 0 : CPU = 0 : MEM = 0.
#Saving pin access data to file ./physical_design/6_stage_afterAll.enc.dat/DLX.apa ...
#
TAT_INFO: ::db::saveSymbolTable REAL = 0 : CPU = 0 : MEM = 0.
TAT_INFO: ::saveCongMap REAL = 0 : CPU = 0 : MEM = 0.
% Begin Save power constraints data ... (date=07/19 02:49:43, mem=2049.8M)
% End Save power constraints data ... (date=07/19 02:49:43, total cpu=0:00:00.0, real=0:00:00.0, peak res=2049.8M, current mem=2049.8M)
high standard low
Generated self-contained design 6_stage_afterAll.enc.dat
#% End save design ... (date=07/19 02:49:55, total cpu=0:00:13.6, real=0:00:15.0, peak res=2050.6M, current mem=2050.6M)
*** Message Summary: 0 warning(s), 0 error(s)
<CMD> setDrawView -quiet -view floorplan
Usage: setDrawView [-help] <mode>
**ERROR: (IMPTCM-48): "-quiet" is not a legal option for command "setDrawView". Either the current option or an option prior to it is not specified correctly.
**ERROR: (IMPSYT-6692): Invalid return code while executing './scripts/scripts_templates/physical_design.tcl' was returned and script processing was stopped. Review the following error in './scripts/scripts_templates/physical_design.tcl' then restart.
**ERROR: (IMPSYT-6693): Error message: ./scripts/scripts_templates/physical_design.tcl: .
<CMD> setDrawView -h
Usage: setDrawView [-help] <mode>
-help # Prints out the command usage
<mode> # Mode (string, required)
<CMD> setDrawView -view floorplan
Usage: setDrawView [-help] <mode>
**ERROR: (IMPTCM-48): "-view" is not a legal option for command "setDrawView". Either the current option or an option prior to it is not specified correctly.
*** Memory Usage v#2 (Current mem = 2625.469M, initial mem = 272.285M) ***
*** Message Summary: 131 warning(s), 14 error(s)
--- Ending "Innovus" (totcpu=0:22:12, real=0:12:13, mem=2625.5M) ---