Loading db file '/home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db'
Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
Warning: There is no defined clock in the design. (PWR-80)
Warning: Design has unannotated primary inputs. (PWR-414)
Warning: Design has unannotated sequential cell outputs. (PWR-415)
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Report : power
-analysis_effort low
Design : DLX
Version: S-2021.06-SP4
Date : Fri Jul 18 23:03:28 2025
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Library(s) Used:
NangateOpenCellLibrary (File: /home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db)
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Design Wire Load Model Library
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DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Global Operating Voltage = 1.1
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000ff
Time Units = 1ns
Dynamic Power Units = 1uW (derived from V,C,T units)
Leakage Power Units = 1nW
Cell Internal Power = 1.4911 mW (70%)
Net Switching Power = 647.6874 uW (30%)
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Total Dynamic Power = 2.1388 mW (100%)
Cell Leakage Power = 334.7412 uW
Information: report_power power group summary does not include estimated clock tree power. (PWR-789)
Internal Switching Leakage Total
Power Group Power Power Power Power ( % ) Attrs
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io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
register 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
sequential 1.3987e+03 0.3248 2.0835e+05 1.6074e+03 ( 64.98%)
combinational 92.4354 647.3650 1.2640e+05 866.1934 ( 35.02%)
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Total 1.4912e+03 uW 647.6898 uW 3.3474e+05 nW 2.4736e+03 uW
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