Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
Warning: Design has unannotated primary inputs. (PWR-414)
Warning: Design has unannotated sequential cell outputs. (PWR-415)
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Report : power
-analysis_effort low
Design : DLX
Version: S-2021.06-SP4
Date : Fri Jul 18 23:06:16 2025
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Library(s) Used:
NangateOpenCellLibrary (File: /home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db)
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Design Wire Load Model Library
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DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Global Operating Voltage = 1.1
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000ff
Time Units = 1ns
Dynamic Power Units = 1uW (derived from V,C,T units)
Leakage Power Units = 1nW
Cell Internal Power = 8.5111 mW (95%)
Net Switching Power = 478.9108 uW (5%)
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Total Dynamic Power = 8.9900 mW (100%)
Cell Leakage Power = 371.4923 uW
Internal Switching Leakage Total
Power Group Power Power Power Power ( % ) Attrs
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io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
register 7.6407e+03 1.5293 1.0710e+05 7.7493e+03 ( 82.78%)
sequential 727.8454 0.0000 1.0306e+05 830.9014 ( 8.88%)
combinational 142.6274 477.3847 1.6134e+05 781.3506 ( 8.35%)
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Total 8.5112e+03 uW 478.9140 uW 3.7149e+05 nW 9.3616e+03 uW
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