Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
Warning: Design has unannotated primary inputs. (PWR-414)
Warning: Design has unannotated sequential cell outputs. (PWR-415)
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Report : power
-analysis_effort low
Design : DLX
Version: S-2021.06-SP4
Date : Fri Jul 18 23:07:01 2025
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Library(s) Used:
NangateOpenCellLibrary (File: /home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db)
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Design Wire Load Model Library
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DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Global Operating Voltage = 1.1
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000ff
Time Units = 1ns
Dynamic Power Units = 1uW (derived from V,C,T units)
Leakage Power Units = 1nW
Cell Internal Power = 17.0223 mW (95%)
Net Switching Power = 957.8102 uW (5%)
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Total Dynamic Power = 17.9801 mW (100%)
Cell Leakage Power = 371.4812 uW
Internal Switching Leakage Total
Power Group Power Power Power Power ( % ) Attrs
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io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
register 1.5281e+04 3.1312 1.0710e+05 1.5392e+04 ( 83.87%)
sequential 1.4557e+03 0.0000 1.0306e+05 1.5587e+03 ( 8.49%)
combinational 285.2550 954.6854 1.6133e+05 1.4013e+03 ( 7.64%)
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Total 1.7022e+04 uW 957.8165 uW 3.7148e+05 nW 1.8352e+04 uW
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