Information: Updating design information... (UID-85)
Warning: Design 'DLX' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
****************************************
Report : timing
-path full
-delay max
-nworst 10
-max_paths 10
Design : DLX
Version: S-2021.06-SP4
Date : Fri Jul 18 23:06:13 2025
****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Startpoint: datapath_inst/fetch_inst/IR_reg[30]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[2]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[30]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[30]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[30] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U5/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[30] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[30] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U37/ZN (NOR2_X1) 0.09 0.23 r
CU_inst/U7/ZN (INV_X1) 0.03 0.26 f
CU_inst/U59/ZN (NAND3_X1) 0.04 0.30 r
CU_inst/U9/ZN (AND2_X1) 0.05 0.35 r
CU_inst/U5/ZN (AOI21_X1) 0.03 0.38 f
CU_inst/alu_func_type_reg[2]/D (DFF_X1) 0.01 0.39 f
data arrival time 0.39
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[2]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.04 0.96
data required time 0.96
--------------------------------------------------------------------------
data required time 0.96
data arrival time -0.39
--------------------------------------------------------------------------
slack (MET) 0.57
Startpoint: datapath_inst/fetch_inst/IR_reg[26]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[2]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[26]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[26]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[26] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U36/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[26] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[26] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U46/ZN (NOR2_X1) 0.10 0.24 r
CU_inst/U59/ZN (NAND3_X1) 0.05 0.29 f
CU_inst/U9/ZN (AND2_X1) 0.05 0.35 f
CU_inst/U5/ZN (AOI21_X1) 0.04 0.38 r
CU_inst/alu_func_type_reg[2]/D (DFF_X1) 0.01 0.39 r
data arrival time 0.39
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[2]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.03 0.97
data required time 0.97
--------------------------------------------------------------------------
data required time 0.97
data arrival time -0.39
--------------------------------------------------------------------------
slack (MET) 0.57
Startpoint: datapath_inst/fetch_inst/IR_reg[28]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[28]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[28]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[28] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U35/ZN (OR2_X1) 0.07 0.16 f
datapath_inst/IR_out[28] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.16 f
CU_inst/IR_IN[28] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.16 f
CU_inst/U45/ZN (OAI21_X1) 0.05 0.21 r
CU_inst/U44/ZN (INV_X1) 0.02 0.23 f
CU_inst/U40/ZN (OAI221_X1) 0.04 0.28 r
CU_inst/U38/ZN (AND3_X1) 0.06 0.34 r
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 f
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.38 f
data arrival time 0.38
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.04 0.96
data required time 0.96
--------------------------------------------------------------------------
data required time 0.96
data arrival time -0.38
--------------------------------------------------------------------------
slack (MET) 0.58
Startpoint: datapath_inst/fetch_inst/IR_reg[28]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[28]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[28]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[28] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U35/ZN (OR2_X1) 0.07 0.16 f
datapath_inst/IR_out[28] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.16 f
CU_inst/IR_IN[28] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.16 f
CU_inst/U45/ZN (OAI21_X1) 0.05 0.21 r
CU_inst/U44/ZN (INV_X1) 0.02 0.23 f
CU_inst/U40/ZN (OAI221_X1) 0.04 0.28 r
CU_inst/U38/ZN (AND3_X1) 0.06 0.34 r
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 f
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.38 f
data arrival time 0.38
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.04 0.96
data required time 0.96
--------------------------------------------------------------------------
data required time 0.96
data arrival time -0.38
--------------------------------------------------------------------------
slack (MET) 0.58
Startpoint: datapath_inst/fetch_inst/IR_reg[28]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[28]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[28]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[28] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U35/ZN (OR2_X1) 0.07 0.16 f
datapath_inst/IR_out[28] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.16 f
CU_inst/IR_IN[28] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.16 f
CU_inst/U45/ZN (OAI21_X1) 0.05 0.21 r
CU_inst/U44/ZN (INV_X1) 0.02 0.23 f
CU_inst/U40/ZN (OAI221_X1) 0.04 0.28 r
CU_inst/U38/ZN (AND3_X1) 0.06 0.34 r
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 f
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.37 f
data arrival time 0.37
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.04 0.96
data required time 0.96
--------------------------------------------------------------------------
data required time 0.96
data arrival time -0.37
--------------------------------------------------------------------------
slack (MET) 0.58
Startpoint: datapath_inst/fetch_inst/IR_reg[28]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[28]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[28]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[28] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U35/ZN (OR2_X1) 0.07 0.16 f
datapath_inst/IR_out[28] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.16 f
CU_inst/IR_IN[28] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.16 f
CU_inst/U45/ZN (OAI21_X1) 0.05 0.21 r
CU_inst/U44/ZN (INV_X1) 0.02 0.23 f
CU_inst/U40/ZN (OAI221_X1) 0.04 0.28 r
CU_inst/U38/ZN (AND3_X1) 0.06 0.34 r
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 f
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.37 f
data arrival time 0.37
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.04 0.96
data required time 0.96
--------------------------------------------------------------------------
data required time 0.96
data arrival time -0.37
--------------------------------------------------------------------------
slack (MET) 0.58
Startpoint: datapath_inst/fetch_inst/IR_reg[30]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[30]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[30]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[30] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U5/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[30] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[30] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U37/ZN (NOR2_X1) 0.09 0.23 r
CU_inst/U40/ZN (OAI221_X1) 0.05 0.28 f
CU_inst/U38/ZN (AND3_X1) 0.05 0.33 f
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 r
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.38 r
data arrival time 0.38
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.03 0.97
data required time 0.97
--------------------------------------------------------------------------
data required time 0.97
data arrival time -0.38
--------------------------------------------------------------------------
slack (MET) 0.59
Startpoint: datapath_inst/fetch_inst/IR_reg[30]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[30]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[30]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[30] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U5/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[30] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[30] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U37/ZN (NOR2_X1) 0.09 0.23 r
CU_inst/U40/ZN (OAI221_X1) 0.05 0.28 f
CU_inst/U38/ZN (AND3_X1) 0.05 0.33 f
CU_inst/U42/ZN (OAI21_X1) 0.03 0.37 r
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.37 r
data arrival time 0.37
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.03 0.97
data required time 0.97
--------------------------------------------------------------------------
data required time 0.97
data arrival time -0.37
--------------------------------------------------------------------------
slack (MET) 0.59
Startpoint: datapath_inst/fetch_inst/IR_reg[30]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[30]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[30]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[30] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U5/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[30] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[30] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U37/ZN (NOR2_X1) 0.09 0.23 r
CU_inst/U40/ZN (OAI221_X1) 0.05 0.28 f
CU_inst/U38/ZN (AND3_X1) 0.05 0.33 f
CU_inst/U42/ZN (OAI21_X1) 0.03 0.36 r
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.37 r
data arrival time 0.37
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.03 0.97
data required time 0.97
--------------------------------------------------------------------------
data required time 0.97
data arrival time -0.37
--------------------------------------------------------------------------
slack (MET) 0.60
Startpoint: datapath_inst/fetch_inst/IR_reg[30]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: CU_inst/alu_func_type_reg[5]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
DLX 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
datapath_inst/fetch_inst/IR_reg[30]/CK (DFFS_X1) 0.00 # 0.00 r
datapath_inst/fetch_inst/IR_reg[30]/Q (DFFS_X1) 0.09 0.09 f
datapath_inst/fetch_inst/IR_out[30] (fetch_stage_OPERAND_SIZE32_I_SIZE32)
0.00 0.09 f
datapath_inst/U5/ZN (OR2_X1) 0.06 0.14 f
datapath_inst/IR_out[30] (datapath_I_SIZE32_OPERAND_SIZE32_NUM_REG5_FUN_SIZE11)
0.00 0.14 f
CU_inst/IR_IN[30] (control_unit_MICROCODE_MEM_SIZE10_FUN_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE15)
0.00 0.14 f
CU_inst/U37/ZN (NOR2_X1) 0.09 0.23 r
CU_inst/U40/ZN (OAI221_X1) 0.05 0.28 f
CU_inst/U38/ZN (AND3_X1) 0.05 0.33 f
CU_inst/U42/ZN (OAI21_X1) 0.03 0.36 r
CU_inst/alu_func_type_reg[5]/D (DFF_X1) 0.01 0.37 r
data arrival time 0.37
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
CU_inst/alu_func_type_reg[5]/CK (DFF_X1) 0.00 1.00 r
library setup time -0.03 0.97
data required time 0.97
--------------------------------------------------------------------------
data required time 0.97
data arrival time -0.37
--------------------------------------------------------------------------
slack (MET) 0.60
1