Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) Warning: Design has unannotated primary inputs. (PWR-414) Warning: Design has unannotated sequential cell outputs. (PWR-415) **************************************** Report : power -analysis_effort low Design : DLX Version: S-2021.06-SP4 Date : Fri Jul 18 23:05:20 2025 **************************************** Library(s) Used: NangateOpenCellLibrary (File: /home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db) Operating Conditions: typical Library: NangateOpenCellLibrary Wire Load Model Mode: top Design Wire Load Model Library ------------------------------------------------ DLX 5K_hvratio_1_1 NangateOpenCellLibrary Global Operating Voltage = 1.1 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000ff Time Units = 1ns Dynamic Power Units = 1uW (derived from V,C,T units) Leakage Power Units = 1nW Cell Internal Power = 4.2556 mW (95%) Net Switching Power = 239.4740 uW (5%) --------- Total Dynamic Power = 4.4950 mW (100%) Cell Leakage Power = 371.5376 uW Internal Switching Leakage Total Power Group Power Power Power Power ( % ) Attrs -------------------------------------------------------------------------------------------------- io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) register 3.8204e+03 0.7828 1.0710e+05 3.9282e+03 ( 80.72%) sequential 363.9227 0.0000 1.0306e+05 466.9787 ( 9.60%) combinational 71.3149 238.6929 1.6139e+05 471.3925 ( 9.69%) -------------------------------------------------------------------------------------------------- Total 4.2556e+03 uW 239.4756 uW 3.7154e+05 nW 4.8666e+03 uW 1