Loading db file '/home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db' Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) Warning: There is no defined clock in the design. (PWR-80) Warning: Design has unannotated primary inputs. (PWR-414) Warning: Design has unannotated sequential cell outputs. (PWR-415) **************************************** Report : power -analysis_effort low Design : DLX Version: S-2021.06-SP4 Date : Fri Jul 18 23:08:16 2025 **************************************** Library(s) Used: NangateOpenCellLibrary (File: /home/mariagrazia.graziano/do/libnangate/NangateOpenCellLibrary_typical_ecsm.db) Operating Conditions: typical Library: NangateOpenCellLibrary Wire Load Model Mode: top Design Wire Load Model Library ------------------------------------------------ DLX 5K_hvratio_1_1 NangateOpenCellLibrary Global Operating Voltage = 1.1 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000ff Time Units = 1ns Dynamic Power Units = 1uW (derived from V,C,T units) Leakage Power Units = 1nW Cell Internal Power = 879.4151 uW (65%) Net Switching Power = 476.5101 uW (35%) --------- Total Dynamic Power = 1.3559 mW (100%) Cell Leakage Power = 367.2615 uW Internal Switching Leakage Total Power Group Power Power Power Power ( % ) Attrs -------------------------------------------------------------------------------------------------- io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) register 6.8585 0.4483 1.0470e+05 112.0117 ( 6.50%) sequential 729.4231 0.0000 1.0302e+05 832.4429 ( 48.31%) combinational 143.1465 476.0632 1.5954e+05 778.7457 ( 45.19%) -------------------------------------------------------------------------------------------------- Total 879.4282 uW 476.5115 uW 3.6726e+05 nW 1.7232e+03 uW 1