// Top module
module OCTAL_COUNTER_TOP (
    CLK_50,  // 50MHz CLOCK
    RSTB,    // Asynchronous RESET (Negative logic)
    oSEG     // 7SEG output
);

    input          CLK_50;
    input          RSTB;
    output [6:0]   oSEG;
    wire   [2:0]   CNT;     // Counter OUTPUT
    
    SCLK_GEN U0(
        .CLK_IN(CLK_50),
        .CLK_OUT(SCLK)
    );
    
    OCTAL_COUNTER U1(
        .CLK(SCLK), 
        .RSTB(RSTB), 
        .oCNT(CNT)
    );
    
    SEG7_LUT U2(
        .iDIG({1'b0,CNT}), 
        .oSEG(oSEG)
    );

endmodule


// Octal (base-8) Counter
module OCTAL_COUNTER (
    CLK, 
    RSTB, 
    oCNT
);
    
    input          CLK;
    input          RSTB;
    output [2:0]   oCNT;
    
    reg [2:0]      CNT;
    
    assign oCNT = CNT;
    
    always @( posedge CLK or negedge RSTB )
        if ( !RSTB )
            CNT <= 0;
        else 
            CNT <= CNT + 3'd1;

endmodule