// Slow clock singnal (SCLK) generator
module SCLK_GEN (
    CLK_IN, 
    CLK_OUT
);

    input          CLK_IN;
    output         CLK_OUT;

    parameter      MSB = 24;
    
    reg [MSB-1:0]  CNT;
    wire           CLK_OUT; 
    
    assign CLK_OUT = CNT[MSB-1];
    
    always @ ( posedge CLK_IN )
        CNT <= CNT + 1'd1;

endmodule