// Top module
module DECIMAL_COUNTER_TOP (
    CLK_50,  // 50MHz CLOCK
    RSTB,    // Asynchronous RESET (Negative logic)
    oSEG     // 7SEG output
);

    input          CLK_50;
    input          RSTB;
    output [6:0]   oSEG;
    wire   [3:0]   CNT;     // Counter OUTPUT
    
    SCLK_GEN U0(
        .CLK_IN(CLK_50),
        .CLK_OUT(SCLK)
    );
    
    DECIMAL_COUNTER U1(
        .CLK(SCLK), 
        .RSTB(RSTB), 
        .oCNT(CNT)
    );
    
    SEG7_LUT U2(
        .iDIG(CNT), 
        .oSEG(oSEG)
    );

endmodule


// Decimal (base-10) Counter
module DECIMAL_COUNTER (
    CLK, 
    RSTB, 
    oCNT
);
    
    input          CLK;
    input          RSTB;
    output [3:0]   oCNT;
    
    reg [3:0]      CNT;
    
    assign oCNT = CNT;
    
    always @( posedge CLK or negedge RSTB )
        if ( !RSTB )
            CNT <= 0;
        else if ( CNT == 4'd9 ) // Please change the condition!
            CNT <= 0;
        else
            CNT <= CNT + 4'd1;

endmodule