module ALU(
        rs1, 
        rs2,
        imm, 
        ALU_out,
        ALU_control,
        operand_B_sel
    );

    input reset;
    input [5:0] ALU_control;
    input operand_B_sel;
    input signed [31:0] rs1, rs2;
    input [31:0] imm;
    output reg signed [31:0] ALU_out;

    wire signed [31:0] Operand_A;
    wire signed [31:0] Operand_B;

    assign Operand_A = rs1;                            
    assign Operand_B = (operand_B_sel) ? imm : rs2;

    always@ *
        begin
            case(ALU_control)
                6'b000000: ALU_out = Operand_A + Operand_B;
                6'b000111: ALU_out = Operand_A - Operand_B;
                6'b000100: ALU_out = Operand_A ^ Operand_B;
                6'b000010: ALU_out = (Operand_A < Operand_B) ? 1:0;
                6'b010000: if (Operand_A > Operand_B | Operand_A == Operand_B) ALU_out = 1;
                6'b000011: if (Operand_A < Operand_B) ALU_out = 0;

            endcase
        end
endmodule