`include "ALU.v"

module ALU_tb;
    reg [5:0] ALU_control;
    reg signed [31:0] rs1, rs2;
    reg [31:0] imm;
    reg operand_B_sel;

    wire signed [31:0] ALU_out;

    ALU uut(
        .ALU_control(ALU_control),
        .rs1(rs1),
        .rs2(rs2),
        .ALU_out(ALU_out),
        .imm(imm),
        .operand_B_sel(operand_B_sel)
    );

    initial begin 
        
        $display("--------------------------");
        operand_B_sel = 0;
        imm = 32'b0;
        ALU_control = 6'b000000;
        rs1 = 2;
        rs2 = 4;

        #10
        $display(" 4 + 2: %d", ALU_out);
        $display("--------------------------");
        ALU_control = 6'b000111;

        #10
        $display(" 4 - 2: %d", ALU_out);
        $display("--------------------------");
        ALU_control = 6'b000100;

        #10
        $display(" 4 ^ 2: %b", ALU_out);
        $display("--------------------------");
        ALU_control = 6'b000010;

        #10
        $display(" 4 < 2: %d", ALU_out);
        $display("--------------------------");
        
        rs1 = 32'h00000020;
        rs2 = 32'h0000000f;
        operand_B_sel = 0;
        ALU_control = 6'b000111;

        #10
        $display("ALU Result 32 - 15: %d",ALU_out);
        $display("--------------------------");

        
        rs1 = 32'hfffffffe;
        rs2 = 32'h0000000f;
        ALU_control = 6'b000010;
        
        #10
        $display("ALU Result -1 < 15 (signed): %d",ALU_out);
        $display("--------------------------");


        operand_B_sel = 1;
        imm = 32'b1;
        ALU_control = 6'b000000;
        rs1 = 4;
        rs2 = 2;

        #10
        $display("ALU Result 4 + imm : %d",ALU_out);
        $display("--------------------------");
        ALU_control = 6'b000100;

        #10
        $display("ALU Result 4 ^ imm : %b",ALU_out);
        $display("--------------------------");
        

    end 

endmodule