module dataMemory(
        clk,
        write,
        addr,
        mem_we,
        read
    );

    input clk;
    input [15:0] addr;
    input [31:0] write;
    input mem_we;
    output [31:0] read;

    localparam depth = 1 << 6;
    reg [31:0] memData [0:depth-1];

    assign read = memData[addr[15:0]];

    always@(posedge clk) begin
        if (mem_we) begin
            memData[addr[15:0]] <= write;
        end 
    end

    

endmodule