`include "Data_memory.v"

module dataMemory_tb;

    reg clk;
    reg [31:0] write;
    reg [15:0] addr;
    reg mem_we;

    wire [31:0] read;

    dataMemory uut(
        .clk(clk),
        .write(write),
        .addr(addr),
        .mem_we(mem_we),
        .read(read)
    );

    always #5 clk = ~clk;

    initial begin 
        $dumpfile("dataMemory_waveform.vcd");
        $dumpvars(0, dataMemory_tb);
        clk = 1'b1;
        addr = 16'b0;
        write = 32'b0;
        mem_we = 1'b0;

        #10
        mem_we = 1'b1;

        #10
        $display("Data address %d: %h", addr, read);
        write = 1;
        addr = 4;

        #10
        $display("Data address %d: %h", addr, read);
        write = 2;
        addr = 8;

        #10
        $display("Data address %d: %h", addr, read);
        mem_we = 1'b0;
        write = 100;
        addr = 8;

        #10
        $display("Data address %d: %h", addr, read);

        
        #20
        $finish;


    end

endmodule