`include "Decoder.v" module Decoder_tb; reg [31:0] instruction; // ALU wires wire branch_op; wire [31:0] imm; wire operand_B_sel; wire [5:0] ALU_control; // Regfile wires wire [4:0] write_addr; // N.B. write_addr.. destination reg address wire [4:0] rs1_addr; // rs1_addr wire [4:0] rs2_addr; // rs2_addr wire we; // Memory wires wire mem_we; // wire [4:0] write_transfer; Decoder uut( .instruction(instruction), .branch_op(branch_op), .imm(imm), .operand_B_sel(operand_B_sel), .ALU_control(ALU_control), .write_addr(write_addr), .rs1_addr(rs1_addr), .rs2_addr(rs2_addr), .we(we), .mem_we(mem_we), // .write_transfer(write_transfer) ); task print_param; begin $display("Time: %0d", $time); $display("instruction: %0b", instruction); $display("rs1_addr: %0b", rs1_addr); $display("rs2_addr: %0b", rs2_addr); $display("write_addr: %0b", write_addr); $display("we: %0b", we); $display("branch_op: %0b", branch_op); $display("imm: %0b", imm); $display("operand_B_sel: %0b", operand_B_sel); $display("ALU_control: %0b", ALU_control); $display("mem_we: %0b", mem_we); // $display("write_transfer -- not yet assigned: %0b", write_transfer); $display("--------------------------------------------------------"); $display("\n"); end endtask initial begin $dumpfile("Decoder_waveform.vcd"); $dumpvars(0, Decoder_tb); $display("--------------------------------------------------------"); instruction = 32'b0; #10 $display("NO Operation: add zero, zero, 0"); print_param(); instruction = 32'b0000000_01100_01011_000_01101_0110011; #10 $display("add a3, a1, a2"); print_param(); instruction = 32'b0100000_01111_01110_000_10000_0110011; #10 $display("sub a6, a4, a5"); print_param(); instruction = 32'b0100000_01111_01110_100_10000_0110011; #10 $display("xor a6, a4, a5"); print_param(); instruction = 32'b0000000_01100_01011_100_01010_0010011; #10 $display("xori a0, a1, imm"); print_param(); instruction = 32'b1100000_01100_01011_101_11111_1100011; #10 $display("bge a4, a5"); print_param(); // to add more load and store tests // don't forget the sel flag end endmodule