module Fetch(
        imm,
        branch_op,
        ALU_control,
        clk,
        reset,
        pc
    );

    input clk;
    input reset;
    input branch_op;
    input [5:0] ALU_control;
    input [31:0] imm;
    output reg [15:0] pc;

    // reg [15:0] pc_reg;
    // assign pc = pc_reg; 
    
    always@(posedge clk)
    begin
        if (reset) begin
            pc <= 0;
        end else if (branch_op) begin
            if(ALU_control == 6'b1) begin
                pc <= pc + imm[15:0]; 
            end else begin
                pc <= pc - imm[15:0];
            end
        end else begin
            pc <= pc + 16'b100;
        end
    end

endmodule


    // get imm and branch_op from control and branch from alu 
    // and do the pc calculations here...
    // branching alu is done in alu