`include "Fetch.v"

module Fetch_tb;

    reg clk;
    reg rst;
    reg branch_op;
    reg [31:0] imm;
    wire reg [15:0] pc;

    Fetch uut(
        .rst(rst),
        .clk(clk),
        .branch_op(branch_op),
        .imm(imm),
        .pc(pc)
    );

    always #5 clk = ~clk;

    initial begin
        $dumpfile("Fetch_waveform.vcd");
        $dumpvars(0, Fetch_tb);
        clk = 1'b1;
        rst = 1'b1;
        imm = 32'b0;
        branch_op = 1'b0;

        #10
        rst = 1'b0;
        

        #10
        $display("pc: %h", pc);

        #10
        imm = 32'b11111111111111111111001101111011;
        branch_op = 1'b0;

        #10
        $display("pc: %h", pc);

        #10
        imm = 32'b11111111111111111111001101111011;
        branch_op = 1'b1;

        #10
        $display("pc: %h", pc);

        #10
        rst = 1'b1;
        imm = 32'b11111111111111111111001101111011;
        branch_op = 1'b1;

        #10
        $display("pc: %h", pc);

        #10
        imm = 32'b11111111111111111111001101111011;
        branch_op = 1'b1;

        #10
        $display("pc: %h", pc);

        $finish;

    end

endmodule