module instMem(
        reset,
        clk,
        pc,
        instruction
    );
    input reset;
    input clk;
    input [15:0] pc;
    output reg [31:0] instruction;

    reg [31:0] inst_mem [0:50];

    initial
    begin
         $readmemh("instmem.dat",inst_mem);
    end

    always@(posedge clk) begin
        if(reset)begin
            instruction <= 1'bx;
        end else begin
            case(pc)
                16'h0000: instruction <= 32'h00A00593;
                16'h0004: instruction <= 32'h00C00693;
                16'h0008: instruction <= 32'h00B2A023;
                16'h000C: instruction <= 32'h00D5A123;
                16'h0010: instruction <= 32'h00D587B3;
                16'h0014: instruction <= 32'h40B78533;
                16'h0018: instruction <= 32'h40F58733;
                16'h001C: instruction <= 32'h00E5A523;
                16'h0020: instruction <= 32'h00052A03;
                16'h0024: instruction <= 32'h00B542B3;
                16'h0028: instruction <= 32'h00A54313;
                16'h002C: instruction <= 32'h00D72CB3;
                16'h0030: instruction <= 32'h00E6AD33;
                16'h0034: instruction <= 32'h00A5C463;
                16'h0038: instruction <= 32'h00B54463;
                16'h003C: instruction <= 32'h0072CB4;
            endcase
        end



        // if (reset)begin
        //     instruction <= 1'bz;
        // end else begin
        // instruction <= inst_mem[pc];
        // end
    end

endmodule