module LSU(
        writeBack_sel,
        rs2,
        ALU_out,
        addr,
        write,
        read,
        write_data
    );

    // Decoder wire
    input writeBack_sel;

    // regfile ports
    input [31:0] rs2;
    output reg [31:0] write_data;

    // memory ports
    input [31:0] read;     // read in mem
    output [31:0] write;

    //ALU wires
    input [31:0] ALU_out;
    

    output [15:0] addr;

    /*

        Store --> Decoder => write enable and rs2_address and immediate value
              --> RegFile => gets rs2 and feeds it to LSU  and feeds rs1 to ALU
              --> ALU => gets rs1 and immediate and gets store adress and feeds it to LSU
              --> LSU => just uses address from ALU and data from regFile rs2 and directs it to memory
              --> dataMemory => whenever write enable is 1 stores rs2 in the given address

        Load  --> Decoder => write back enable and rs1_address and immediate value
              --> RegFile => gets rs1 and feeds it to ALU
              --> ALU => gets rs1 and immediate and gets load address and feeds it to LSU
              --> LSU => just uses address from ALU and whenever write back is enable it loads data from memory to destination register
              --> dataMemory => nothing except loads data from the given address
 
    */
    
    assign addr = ALU_out[15:0];
    assign write = rs2;

    always@(*) begin 

        if(writeBack_sel) begin
            write_data <= read;
        end else begin
            write_data <= ALU_out;
        end

    end  

endmodule