`include "LSU.v"

module LSU_tb;

    reg writeBack_sel;
    reg [31:0] rs2;
    reg [31:0] ALU_out;
    reg [31:0] rdata;

    wire [15:0] addr;
    wire [31:0] write;
    wire [31:0] write_data;

    LSU uut(
        .writeBack_sel(writeBack_sel),
        .rs2(rs2),
        .ALU_out(ALU_out),
        .read(rdata),
        .addr(addr),
        .write(write),
        .write_data(write_data)
    );

    initial begin
        rs2 = 32'b1010;
        ALU_out = 32'b11111;
        writeBack_sel = 0;
        rdata = 5;

        #10
        $display("Write_data %d:", write_data);
        $display("write %d:", write);

        writeBack_sel = 1;

        #10
        $display("Write_data %d:", write_data);
        $display("write %d:", write);

    end
endmodule