module regFile(
        clk, 
        reset,
        rs1_addr, 
        rs2_addr, 
        write_addr, 
        we, 
        write_data, 
        rs1, 
        rs2
    );

    input clk, reset;
    input [4:0] rs1_addr;
    input [4:0] rs2_addr;
    input [4:0] write_addr;
    input signed [31:0] write_data;
    input we;
    output reg signed [31:0] rs1;
    output reg signed [31:0] rs2;

    reg [31:0] Reg_mem [0:31];

    /*

    initial begin 
         for(integer i = 0; i<32; i = i + 1)
                begin
                    Reg_mem [i] <= 0;
                end 
    end 

    */

    always@(rs1_addr, rs2_addr)
        begin: READ
            rs1 <= Reg_mem[rs1_addr];
            rs2 <= Reg_mem[rs2_addr];
        end 
    
    always@(posedge clk)
        begin: WRITE
            if(reset) begin
                for(integer i = 0; i<32; i = i + 1)
                begin
                    Reg_mem [i] <= 0;
                end 
            end else begin
                if (we) begin
                    Reg_mem[write_addr] <= write_data;
                end
            end
        end 

endmodule