`include "RegFile.v"

module regFile_tb;

    reg clk;
    reg reset;
    reg [4:0] rs1_addr;
    reg [4:0] rs2_addr;
    reg [4:0] write_addr;
    reg [31:0] write_data;
    reg we;
    wire [31:0] rs1;
    wire [31:0] rs2;
    integer i;

    regFile uut (
        .clk(clk),
        .reset(reset),
        .we(we),
        .rs1_addr(rs1_addr),
        .rs2_addr(rs2_addr),
        .write_addr(write_addr),
        .write_data(write_data),
        .rs1(rs1),
        .rs2(rs2)
    );

    always #5 clk = ~clk;

    initial begin
        $dumpfile("regFile_waveform.vcd");
        $dumpvars(0, regFile_tb);
        clk = 1'b0;
        reset = 1'b1;
        rs1_addr = 0;
        rs2_addr = 0;
        write_addr = 0;
        write_data = 0;
        we = 1'b1;
        i = 0;

        #10
        reset = 1'b0;
        rs1_addr = 5'b1;
        rs2_addr = 5'b11111;

        #10
        we = 1'b1;
        write_addr = 5'b1;
        write_data = 32'b1;
        for(i=0; i<32; i=i+1) begin
            $display("Register %d: %h", i, uut.Reg_mem[i]);
        end

        #10
        we = 1'b1;
        write_addr = 5'b11110;
        write_data = 32'b111111;
        for(i=0; i<32; i=i+1) begin
            $display("Register %d: %h", i, uut.Reg_mem[i]);
        end

        #10
        write_addr = 5'b11101;
        write_data = 32'b111101;
        for(i=0; i<32; i=i+1) begin
            $display("Register %d: %h", i, uut.Reg_mem[i]);
        end

        #10
        $finish;

    end

endmodule