`include "ALU.v"
`include "Decoder.v"
`include "Fetch.v"
`include "LSU.v"
`include "Data_memory.v"
`include "RegFile.v"
`include "Instruction_memory.v"


module top(
    clk,
    reset,
    data
    );

    input clk;
    input reset;
    output [31:0] data;


    // Wires from fetch_module
    wire [15:0] pc;

    // Decode wires
    wire [31:0] instruction;
    wire branch_op;
    wire signed [31:0] imm;
    wire operand_B_sel;

    // RegFile wires
    wire [4:0] rs1_addr;
    wire [4:0] rs2_addr;
    wire [4:0] write_addr;
    wire we;
    wire signed [31:0] rs1;
    wire signed [31:0] rs2;
    wire signed [31:0] write_data;


    // ALU Wires

    wire [5:0] ALU_control;
    wire signed [31:0] ALU_out;

    // LSU wires

    wire [15:0] addr;
    wire signed [31:0] write;

    // Memory Wires
    wire mem_we;
    wire signed [31:0] read;


    // Writeback Wires
    wire writeBack_sel;

    // Final output
    assign data = write_data;


    instMem instMem_inst(
        .reset(reset),
        .clk(clk),
        .pc(pc),
        .instruction(instruction)
    );

    Fetch fetch_inst(
        .reset(reset),
        .clk(clk),
        .branch_op(branch_op),
        .imm(imm),
        .pc(pc)
        );


    Decoder decoder_inst(
        .instruction(instruction),
        .branch_op(branch_op),
        .imm(imm),
        .operand_B_sel(operand_B_sel),
        .ALU_control(ALU_control),
        .write_addr(write_addr),
        .rs1_addr(rs1_addr),
        .rs2_addr(rs2_addr),
        .writeBack_sel,
        .we(we),
        .mem_we(mem_we)
       // .write_transfer(write_transfer)
        );

    regFile regFile_inst(
        .clk(clk),
        .reset(reset),
        .we(we),
        .rs1_addr(rs1_addr),
        .rs2_addr(rs2_addr),
        .write_addr(write_addr),
        .write_data(write_data),
        .rs1(rs1),
        .rs2(rs2)
    );

    LSU LSU_inst(
        .writeBack_sel(writeBack_sel),
        .rs2(rs2),
        .ALU_out(ALU_out),
        .read(read),
        .addr(addr),
        .write(write),
        .write_data(write_data)
    );


    ALU ALU_inst(
        .ALU_control(ALU_control),
        .rs1(rs1),
        .rs2(rs2),
        .ALU_out(ALU_out),
        .imm(imm),
        .operand_B_sel(operand_B_sel)
    );


    dataMemory dataMemory_inst(
        .clk(clk),
        .write(write),
        .addr(addr),
        .mem_we(mem_we),
        .read(read)
    );


endmodule