`include "Top.v"

module top_tb;
    reg clk;
    reg reset;

    wire signed [31:0] data;

    integer x;

    top uut(
        .clk(clk),
        .reset(reset),
        .data(data)
    );

    always #5 clk = ~clk;

    task print_state;
        begin
            $display("Time:\t%0d", $time);
            for( x=0; x<32; x=x+1) begin
                 $display("Register %d: %h", x, uut.regFile_inst.Reg_mem[x]);
            end
            $display("--------------------------------------------------------------------------------");

            for( x=0; x<50; x=x+1) begin
                 $display("Data Memory %d: %h", x, uut.dataMemory_inst.memData[x]);
            end
            $display("--------------------------------------------------------------------------------");
            $display("\n\n");
        end
    endtask

    initial begin
        $dumpfile("waveform_top_tb.vcd");
        $dumpvars(0, top_tb);
        clk = 1'b1;
        reset = 1'b1;
        uut.regFile_inst.Reg_mem[0] = 32'd0;
       

        #1
        #10
        reset = 1'b0;

        #250
        print_state();

        $finish;
    end


endmodule