module counterID
    # (
           parameter digit_0 = 4'b1,
              digit_1 = 4'b0,
              digit_2 = 4'b0,
              digit_3 = 4'b0,
              digit_4 = 4'b0100,
              digit_5 = 4'b0011,
              digit_6 = 4'b0011,
              digit_7 = 4'b0111,
              digit_8 = 4'b0100 )
    (
    clk,
    reset,
    en_up,
    counter
   );
 

    input clk;
    input reset;
    input [1:0] en_up;
    // input [1,0] en_down;
    output wire [3:0] counter;
    
    wire [4:0] data [0:8]; 



    assign data[0] = digit_0;
    assign data[1] = digit_1;
    assign data[2] = digit_2;
    assign data[3] = digit_3;
    assign data[4] = digit_4;
    assign data[5] = digit_5;
    assign data[6] = digit_6;
    assign data[7] = digit_7;
    assign data[8] = digit_8;


    reg [3:0] N;


    // always@ * begin
    //     if (en_up==1'b1 && N==4'b0) begin
    //         N <= N+1;
    //     end else if (en_down) begin
    //         en_up = 1'b0;
    //     end else begin
    //         en_up = 1'b0;
    //         en_down = 1'b0;
    //     end 
    // end

    assign counter = data[N];


    always@(posedge clk) begin
        if (reset) begin

            if(en_up == 1'b1) begin
                N <= 4'd0;
            end else begin
                N <= 4'd8;
            end
  
        end else begin

           if (en_up == 1'b0) begin

            //   counter <= data[N];
               
               if (N == 0)begin
                   N <= 4'd8;
               end else begin
                   N <= N-1;
               end

           end else begin

            //   counter <= data[N]; 

               if(N == 4'd8)begin
                   N <= 0;    
               end else begin
                   N <= N+1;
               end
               
           end

         end
    end


endmodule