`include "counterID.sv"

module counterID_tb;

    reg clk;
    reg reset;
    reg [1:0] en_up;
    wire [3:0] counter;

  //  counterTrial #(data = {1,2,3,4,5,6,7,8,9});

    counterID 
    #(
              .digit_0 (4'b1),
              .digit_1 (4'b0),
              .digit_2 (4'b0),
              .digit_3 (4'b0),
              .digit_4 (4'b0100),
              .digit_5 (4'b0011),
              .digit_6 (4'b0011),
              .digit_7 (4'b0111),
              .digit_8 (4'b0100)) uut(
        .clk(clk),
        .reset(reset),
        .en_up(en_up),
        .counter(counter)
    );

    always #5 clk = ~clk;

    initial begin
        $dumpfile("counterID_wf.vcd");
        $dumpvars(0, counterID_tb);
        clk = 1'b1;
        reset = 1'b1;
        en_up = 0;


        #15
        reset = 1'b0;

       // #75
        #80
        en_up = 1;


        #85
        reset = 1;

	      #25
        en_up = 0;

        #100
        $finish;

    end


endmodule