TNSM_Latency_Prediction / code / parser / 0_baseline / ingress.p4
ingress.p4
Raw
control Ingress(
                /* User */
                inout my_ingress_headers_t                       hdr,
                inout my_ingress_metadata_t                      meta,
                /* Intrinsic */
                in    ingress_intrinsic_metadata_t               ig_intr_md,
                in    ingress_intrinsic_metadata_from_parser_t   ig_prsr_md,
                inout ingress_intrinsic_metadata_for_deparser_t  ig_dprsr_md,
                inout ingress_intrinsic_metadata_for_tm_t        ig_tm_md)
{
    apply{

        hdr.ts_ingress.setValid();
        hdr.ts_ingress.ts1 = ig_intr_md.ingress_mac_tstamp;
        hdr.ts_ingress.ts2 = ig_intr_md.global_tstamp;

        // static output port
        ig_tm_md.ucast_egress_port = bit<9>48;
    }

}