TNSM_Latency_Prediction / code / parser / 19_testcase3_edge_parser / ingress.p4
ingress.p4
Raw
control Ingress(
                /* User */
                inout my_ingress_headers_t                       hdr,
                inout my_ingress_metadata_t                      meta,
                /* Intrinsic */
                in    ingress_intrinsic_metadata_t               ig_intr_md,
                in    ingress_intrinsic_metadata_from_parser_t   ig_prsr_md,
                inout ingress_intrinsic_metadata_for_deparser_t  ig_dprsr_md,
                inout ingress_intrinsic_metadata_for_tm_t        ig_tm_md)
{
   
    apply{

        hdr.ts_ingress.setValid();
        hdr.ts_ingress.ts1 = ig_intr_md.ingress_mac_tstamp;
        hdr.ts_ingress.ts2 = ig_prsr_md.global_tstamp;

        // static output port
        ig_tm_md.ucast_egress_port = (bit<9>)188;
    #ifdef CHECK
        if(hdr.mpls[2].isValid() && hdr.eompls.isValid() && hdr.inner_ethernet.isValid()){
            hdr.check.setValid();
            hdr.check.a = 0x12121212;
            hdr.check.b = 0x34343434;
            hdr.check.c = 0x56565656;
            hdr.check.d = 0x78787878;
        }
    #endif
    }

}