/* CPEN 211 Lab 3 */
/* Danial Jaber and Prayetnaa Kansakar*/

//defining states as 4 bit binary
`define SW 4
`define SA 4'b0000
`define SB 4'b0001
`define SC 4'b0010
`define SD 4'b0011
`define SE 4'b0100
`define SF 4'b0101
`define SG 4'b0111
`define SH 4'bxxxx
`define SI 4'bxxxx
`define SJ 4'bxxxx
`define SK 4'bxxxx
`define SL 4'bxxxx
`define SM 4'b1111

//defining decimal numbers as 4 bit binary
`define d0 4'b0000
`define d1 4'b0001
`define d2 4'b0010
`define d3 4'b0011
`define d4 4'b0100
`define d5 4'b0101
`define d6 4'b0110
`define d7 4'b0111
`define d8 4'b1000
`define d9 4'b1001
`define d10 4'b1010
`define d11 4'b1011
`define d12 4'b1100
`define d13 4'b1101
`define d14 4'b1110
`define d15 4'b1111

module lab3_top(SW,KEY,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,LEDR);
  input [9:0] SW;
  input [3:0] KEY;
  output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
  output [9:0] LEDR; 

  wire clk;
  assign clk = ~KEY[0]; //inverts the clock input and assigns it to the rightmost button
  wire reset;
  assign reset = ~KEY[3]; //inverses the reset input and assigns it to the leftmost button
 
  wire [3:0] digit;
  assign digit = SW[3:0]; //sets the system to read the first 4 of 10 switches for number inputs
  wire [3:0] state;

  lab3_msm msm(clk, reset, digit, state); 
  lab3_dec47 dec47(digit, state, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5); 

endmodule

//instantiates the moore's machine finite state machine
module lab3_msm(clk,reset,digit,state);
  input clk, reset;
  input [3:0] digit;
  output [3:0] state; 
  reg [3:0] state;
  reg [3:0] present_state;

always@(posedge clk, posedge reset) begin //runs upon positive input of the clock or reset
	if (reset) begin
		present_state = `SA; end
	else begin
		case(present_state)
			`SA: if(digit == 4'b0111)
				present_state = `SB;
			     else
				present_state = `SH;
			`SB: if(digit == 4'b0110)
				present_state = `SC;
			     else
				present_state = `SI;
			`SC: if(digit == 4'b0110)
				present_state = `SD;
			     else
				present_state = `SJ;
			`SD: if(digit == 4'b1000)
				present_state = `SE;
			     else
				present_state = `SK;
			`SE: if(digit == 4'b0001)
				present_state = `SF;
			     else
				present_state = `SL;
			`SF: if(digit == 4'b1001)
				present_state = `SG;
			     else
				present_state = `SM;
			`SH: present_state = `SI;
			`SI: present_state = `SJ;
			`SJ: present_state = `SK;
			`SK: present_state = `SL;
			`SL: present_state = `SM;
			default: present_state = 4'bxxxx;
		endcase
	end
	state = present_state;
end
endmodule

//instantiates the 4:7 decoder
module lab3_dec47(digit, state, H0, H1, H2, H3, H4, H5);
    input [3:0] digit;
    input [3:0] state;
    output reg [6:0] H0, H1 ,H2 ,H3 ,H4 ,H5;     

always @(digit,state) begin //runs upon changes to binary switch digits or moore's state
	case(digit) 
        	`d0: begin H0 = 7'b1000000;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
	 		   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end
            
        	`d1: begin H0 = 7'b1111001;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d2: begin H0 = 7'b0100100;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d3: begin H0 = 7'b0110000;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d4: begin H0 = 7'b0011001;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d5: begin H0 = 7'b0010010;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d6: begin H0 = 7'b0000010;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d7: begin H0 = 7'b1111000;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d8: begin H0 = {7{1'b0}};
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d9: begin H0 = 7'b0010000;
              		   H1 = {7{1'b1}};
			   H2 = {7{1'b1}};
			   H3 = {7{1'b1}};
			   H4 = {7{1'b1}};
			   H5 = {7{1'b1}}; end

        	`d10, `d11, `d12, `d13, `d14, `d15: begin H0 = 7'b0101111;
              		       			          H1 = 7'b1000000;
 							  H2 = 7'b0101111;
 							  H3 = 7'b0101111;
						          H4 = 7'b0000110;
 							  H5 = {7{1'b1}}; end
		default: begin H0 = {7{1'bx}};
			       H1 = {7{1'bx}};
			       H2 = {7{1'bx}};
			       H3 = {7{1'bx}};
			       H4 = {7{1'bx}};
			       H5 = {7{1'bx}}; end
	endcase 

	case(state)
		`SG: begin H0 = 7'b0101011;
                	   H1 = 7'b0000110;
        	           H2 = 7'b0001100;
        	           H3 = 7'b1000000;
        	           H4 = {7{1'b1}};
        	           H5 = {7{1'b1}}; end //outputs OPEn

		`SM: begin H0 = 7'b0100001;
        	           H1 = 7'b0000110;
        	           H2 = 7'b0010010;
        	           H3 = 7'b1000000;
        	           H4 = 7'b1000111;
        	           H5 = 7'b0000111; end //outputs CLOSEd
	endcase
end
endmodule