/* CPEN 211 Lab 3 Testbench */
/* Prayetnaa Kansakar and Danial Jaber*/

`timescale 1 ps/1 ps

// 4 bit binary state encoding definitions
`define Sa 4'b0000 // reset state
`define Sb 4'b0001 // 7
`define Sc 4'b0010 // 6
`define Sd 4'b0011 // 6
`define Se 4'b0100 // 8
`define Sf 4'b0101 // 1
`define Sg 4'b0111 // 9 OPEn
`define Sh 4'b1111 // 
`define Si 4'b1111 // 
`define Sj 4'b1111 // 
`define Sk 4'b1111 // 
`define Sl 4'b1111 // 
`define Sm 4'b1111 // CLOSEd

module lab3_top_tb ();
  // no inputs or outputs because this is a testbench

  // inputs are reg
  reg [3:0] sim_KEY;
  reg [9:0] sim_SW;
  reg err;

  // outputs are wire
  wire [9:0] sim_LEDR;
  wire [6:0] sim_HEX0, sim_HEX1, sim_HEX2, sim_HEX3, sim_HEX4, sim_HEX5;

  // assigning the device under test
  lab3_top dut(.SW(sim_SW), .KEY(sim_KEY), .HEX0(sim_HEX0), .HEX1(sim_HEX1), 
		.HEX2(sim_HEX2), .HEX3(sim_HEX3), .HEX4(sim_HEX4), .HEX5(sim_HEX5), .LEDR(sim_LEDR));

// initial block for clock
initial begin 
  // set clock to zero first
  sim_KEY[0] = 1'b0; #5; // the first rising edge of clock would be at time 5

	forever begin
	  sim_KEY[0] = 1'b1; #5;  // positive edge of clock
	  sim_KEY[0] = 1'b0; #5;  // negative edge of clock
	end
end

// initial block for KEY[3] (reset), error, SW signals
initial begin

// testing for correct case

  sim_KEY[3] = 1'b0;  // set reset to zero at first
  sim_SW[9:0] = {10{1'b0}};  // set SW signals to zero
  err = 1'b0;

  #1; // delay 1 ps to ensure current SW signals are read correctly

	// check if current state is in expected state according to finite state machine specification
	if (lab3_top_tb.dut.state !== `Sa) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sa);

		err = 1'b1; // error occured at this time stamp
  	end

  #9;  // delay 9 ps to ensure current SW signals are read correctly

  sim_KEY[3] = 1'b1;  // set reset to HIGH
  sim_SW[9:0] = 10'b0000000111; // set SW[3:0] to decimal number 7 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Sb) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sb);

		err = 1'b1;
  	end

  #9; 

  sim_SW[9:0] = 10'b0000000110; // set SW[3:0] to decimal number 6 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Sc) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sc);

		err = 1'b1;
  	end

  #9; 

  sim_SW[9:0] = 10'b0000000110; // set SW[3:0] to decimal number 6 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Sd) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sd);

		err = 1'b1;
  	end

  #9; 

  sim_SW[9:0] = 10'b0000001000; // set SW[3:0] to decimal number 8 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Se) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Se);

		err = 1'b1;
  	end

  #9; 

  sim_SW[9:0] = 10'b0000000001; // set SW[3:0] to decimal number 1 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Sf) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sf);

		err = 1'b1;
  	end

  #9; 

  sim_SW[9:0] = 10'b0000001001; // set SW[3:0] to decimal number 9 in 4 bit binary
  err = 1'b0;

  #1;

	if (lab3_top_tb.dut.state !== `Sg) begin
		$display("ERROR ** state is %b, expected %b",
			lab3_top_tb.dut.state, `Sg);

		err = 1'b1;
  	end

  #9; 

	if(~err) $display("PASSED");
          $stop;
  end
endmodule