module ALU_tb();

reg err;
reg clk;
reg [15:0] Ain, Bin;
reg [1:0] ALUop;
wire [15:0] out;
wire Z;

ALU DUT(Ain, Bin, ALUop, out, Z);

task alucheck;
    input [15:0] expected_out;
    input expected_Z;
begin
    if(ALU_tb.DUT.out !== expected_out) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.out, expected_out);
        err = 1'b1; end

    if(ALU_tb.DUT.Z !== expected_Z) begin
        $display("ERROR: Z is %b, expected %b",
        ALU_tb.DUT.Z, expected_Z);
        err = 1'b1; end
end 
endtask

initial begin
    clk = 1'b0; #5;
    forever begin
        clk = 1'b1; #5;
        clk = 1'b0; #5;
    end
end

initial begin
    $display("Checking addition of 6+3");
    Ain = 16'b0000000000000110;  
    Bin = 16'b0000000000000011;
    ALUop = 2'b00; err = 1'b0; #10
    alucheck(16'b0000000000001001, 1'b0);

    $display("Checking subtraction of 7-1");
    Ain = 16'b0000000000000111;  
    Bin = 16'b0000000000000001;
    ALUop = 2'b01; #10
    alucheck(16'b0000000000000110, 1'b0);

    $display("Checking subtraction of 8-8");
    Ain = 16'b0000000000001000;  
    Bin = 16'b0000000000001000;
    ALUop = 2'b01; #10
    alucheck(16'b0000000000000000, 1'b1);

    $display("Checking anding of inputs 5 and 3");
    Ain = 16'b0000000000000101;  
    Bin = 16'b0000000000000011;
    ALUop = 2'b10; #10
    alucheck(16'b0000000000000001, 1'b0);

    $display("Checking the inverse of input 1"); 
    Bin = 16'b0000000000000001;
    ALUop = 2'b11; #10
    alucheck(16'b1111111111111110, 1'b0);

    if(~err) $display("PASSED");
    else $display("FAILED");
   // $stop;
#450;

end
endmodule