module shifter_tb();

    // signals for testbench
    reg err;
    reg clk;
    reg [15:0] in;
    reg [1:0] shift;
    wire [15:0] sout;

shifter DUT(in, shift, sout); //reference to shifter module for testbenching

task shiftercheck;
    input [15:0] expected_sout; //providing expected shifter output
begin
    if(shifter_tb.DUT.sout !== expected_sout) begin  //outputs error of shifter output does not match expected shifter output
        $display("ERROR: output is %b, expected %b",
        shifter_tb.DUT.sout, expected_sout);
        err = 1'b1; end
end
endtask

initial begin
    clk = 1'b0; #5; //repeating clock in 5ps second intervals
    forever begin
        clk = 1'b1; #5;
        clk = 1'b0; #5;
    end
end

initial begin
    $display("Checking no shift input");
    in = 16'b0000000011110101; //245
    shift = 2'b00; err = 1'b0; #10; //no shift
    shiftercheck(16'b0000000011110101); //245

    $display("Checking 1-bit logical left shift");
    in = 16'b0000000000000101; //5
    shift = 2'b01;#10; //shift left
    shiftercheck(16'b0000000000001010); //multiplied by 2 -> 10

    $display("Checking 1-bit logical right shift");
    in = 16'b0000000000011101; //29
    shift = 2'b10;#10; //shift right
    shiftercheck(16'b0000000000001110); //divided by 2 (remainder lost) --> 14

    $display("Checking 1-bit logical right shift and MSB assign 1");
    in = 16'b1000000001101000; //104
    shift = 2'b11;#10; //right shift with MSB maintained
    shiftercheck(16'b1100000000110100); //large number due to MSB maintained --> 49204s

    if(~err) $display("PASSED");
    else $display("FAILED");

#460;

end
endmodule