/* CPEN 211 Lab 6: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* cpu.v */

module cpu(clk,reset,s,load,in,out,N,V,Z,w);
    
    //i/o signals
    input clk, reset, s, load;
    input [15:0] in;
    output [15:0] out;
    output N, V, Z, w;
    wire [15:0] ireg;
    wire [15:0] sximm5, sximm8;
    wire [2:0] writenum, readnum, nsel, opcode;
    wire [1:0] shift, ALUop, op;
    wire write, clk, loada, loadb, loadc, loads, asel, bsel;
    wire [3:0] vsel;

vDFFE #(16) in_reg(.clk(clk), .load(load), .in(in), .out(ireg)); //instantiation for instruction register

instruction_dec in_dec(.ireg(ireg), .nsel(nsel), .opcode(opcode), .op(op), .ALUop(ALUop), .sximm5(sximm5), .sximm8(sximm8), .shift(shift), .readnum(readnum), .writenum(writenum)); //instantiation for instruction decoder

datapath DP(.sximm5(sximm5), .sximm8(sximm8), .writenum(writenum), .write(write), .readnum(readnum), .clk(clk),
                .loada(loada), .loadb(loadb), .loadc(loadc), .loads(loads), .vsel(vsel), .asel(asel), .bsel(bsel), 
                .shift(shift), .ALUop(ALUop), .Z_out({N,V,Z}), .datapath_out(out)); //instantiation for datapath

fsm_controller CTRL(.clk(clk), .reset(reset), .s(s), .opcode(opcode), .op(op), .write(write),
    .loada(loada), .loadb(loadb), .loadc(loadc), .loads(loads), .asel(asel), .bsel(bsel), .vsel(vsel), .nsel(nsel), .w(w)); //instantiation for fsm controller

endmodule