module cpu_tb(); //USE HIERARCHICAL NAMING HERE AND HERE ONLY

reg err;
reg clk, reset, s, load;
reg [15:0] in, out;
reg N, V, Z, w;

cpu DUT(clk, reset, s, load, in, out, N, V, Z, w);

task cpucheck;
    input [15:0] expected_out;
    input expected_N;
    input expected_V;
    input expected_Z;
    input expected_w;
begin
    
    if(cpu_tb.DUT.out !== expected_out) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.out, expected_out);
        err = 1'b1; end

    if(cpu_tb.DUT.N !== expected_N) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.N, expected_N);
        err = 1'b1; end

    if(cpu_tb.DUT.V !== expected_V) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.V, expected_V);
        err = 1'b1; end

    if(cpu_tb.DUT.Z !== expected_Z) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.Z, expected_Z);
        err = 1'b1; end

    if(cpu_tb.DUT.w !== expected_w) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.w, expected_w);
        err = 1'b1; end
end
endtask

initial begin
    clk = 1'b0; #5;
    forever begin
        clk = 1'b1; #5;
        clk = 1'b0; #5;
    end
end

initial begin
    err = 1'b0
    //RESET CHECK HERE

    $display("Checking ");
    reset = 1'b0; s = 1'b1; load = 1'b1;
    input = 16'b0000000000000000; #10
    cpucheck(16'b0000000000000000, 1'b0, 1'b0, 1'b0, 1'b0);
#20
    $display("Checking ...");
    reset = 1'b0; s = 1'b1; load = 1'b1;
    input = 16'b0000000000000000; #10
    cpucheck(16'b0000000000000000, 1'b0, 1'b0, 1'b0, 1'b0);
#20

    if(~err) $display("PASSED");
    else $display("FAILED");
    $stop;

//Delay to reach for 500 picoseconds

end
endmodule