// testbench for LAB6 cpu MOV function


// OLD state encoding

// `define Wait 3'b000
// `define Decode 3'b001
// `define GetA 3'b010
// `define GetB 3'b011
// `define ExecuteOperation 3'b100
// `define WriteReg 3'b101
// `define Writelmm 3'b110

// NEW STATE ENCODING
`define Wait 4'b0000
`define Decode 4'b0001
`define GetA 4'b0010
`define GetB 4'b0011

`define MOV_Rd_Rm 4'b0100
`define ADD 4'b0101
`define CMP 4'b0110
`define AND 4'b0111 
`define MVN 4'b1000

`define WriteReg 4'b1001
`define Writelmm 4'b1010



module cpu_tb(); // testbench so no I/O

reg sim_clk;
reg sim_reset;
reg sim_s;
reg sim_load;
reg [15:0] sim_in;
// outputs are wires
wire [15:0] sim_out; 
wire sim_N, sim_V, sim_Z, sim_w;

reg err; // error check

// INSTANTIATION

cpu DUT(
    .clk(sim_clk),
    .reset(sim_reset),
    .s(sim_s),
    .load(sim_load),
    .in(sim_in),
    .out(sim_out),
    .N(sim_N),
    .V(sim_V),
    .Z(sim_Z),
    .w(sim_w)  
);

//TASK

task output_checker;

    // Wires coming out of the status register in datapath
    input expected_N; // negative 
    input expected_V; // overflow
    input expected_Z; // zero

    //input [2:0] expected_state;
    input [3:0] expected_state;

    // input [15:0] expected_IR_out;
    input [15:0] expected_register_value_R0;
    input [15:0] expected_register_value_R1;
    input [15:0] expected_register_value_R2;
    input [15:0] expected_register_value_R3;
    input [15:0] expected_register_value_R4;
    input [15:0] expected_register_value_R5;
    input [15:0] expected_register_value_R6;
    input [15:0] expected_register_value_R7;

    input expected_w; // 1 if in wait, 0 otherwise


begin
    if (cpu_tb.DUT.N !== expected_N) begin
        $display("ERROR, *** N is %b, expected %b", cpu_tb.DUT.N, expected_N);
        
        err = 1'b1; // raise error
    
    end

    if (cpu_tb.DUT.V !== expected_V) begin
        $display("ERROR, *** V is %b, expected %b", cpu_tb.DUT.V, expected_V);
        
        err = 1'b1; // raise error
    
    end

    if (cpu_tb.DUT.Z !== expected_Z) begin
        $display("ERROR, *** Z is %b, expected %b", cpu_tb.DUT.Z, expected_Z);
        
        err = 1'b1; // raise error
    
    end

    if (cpu_tb.DUT.SM.state !== expected_state) begin
        $display("ERROR, *** state is %b, expected %b", cpu_tb.DUT.SM.state, expected_state);
        
        err = 1'b1; // raise error
    
    end

    // if (cpu_tb.DUT.IR_out !== expected_IR_out) begin
    //     $display("ERROR, *** state is %b, expected %b", cpu_tb.DUT.IR_out, expected_IR_out);
        
    //     err = 1'b1; // raise error
    
    // end

    if (sim_w !== expected_w) begin
        $display("ERROR, *** w is %b, expected %b", sim_w, expected_w);
        
        err = 1'b1; // raise error
    
    end

    if (cpu_tb.DUT.DP.REGFILE.R0 !== expected_register_value_R0) begin
        $display("ERROR, *** register 0 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R0, expected_register_value_R0);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R1 !== expected_register_value_R1) begin
        $display("ERROR, *** register 1 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R1, expected_register_value_R1);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R2 !== expected_register_value_R2) begin
        $display("ERROR, *** register 2 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R2, expected_register_value_R2);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R3 !== expected_register_value_R3) begin
        $display("ERROR, *** register 3 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R3, expected_register_value_R3);

        err = 1'b1; // raise error
    end
    
     if (cpu_tb.DUT.DP.REGFILE.R4 !== expected_register_value_R4) begin
        $display("ERROR, *** register 4 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R4, expected_register_value_R4);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R5 !== expected_register_value_R5) begin
        $display("ERROR, *** register 5 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R5, expected_register_value_R5);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R6 !== expected_register_value_R6) begin
        $display("ERROR, *** register 6 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R6, expected_register_value_R6);

        err = 1'b1; // raise error
    end

     if (cpu_tb.DUT.DP.REGFILE.R7 !== expected_register_value_R7) begin
        $display("ERROR, *** register 7 is %b, expected %b", cpu_tb.DUT.DP.REGFILE.R7, expected_register_value_R7);

        err = 1'b1; // raise error
    end

        
end
endtask


// START DEBUG

initial begin       // clock timing
    sim_clk = 1'b0; #5;
    forever begin
        sim_clk = 1'b1; #5;
        sim_clk = 1'b0; #5;

    end

end


initial begin


err = 1'b0; // set error to 0

sim_reset = 1'b1; // push reset

#10; // wait for clk

sim_reset = 1'b0; // deassert reset


$display("--- Checking MOV Rn#<im8>, MOV R0, #7 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1101000000000111;                // MOV R0, #7 instruction encoded
sim_load = 1'b1;
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait stat

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> Writelmm");
#10; 
output_checker(1'bx,1'bx,1'bx,`Writelmm,
                16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Writelmm, R0 undefined, w = 0 as not in wait state
                                                     // R0 is undefined because of the delay of change in 'state', 
                                                     // causing 'readnum' change delay which is no longer on rising edge of clock
                                                     // Therefore R0 will be updated on next rising edge of clock

$display("Checking Writelmm -> Wait ... Checking R0 = 7");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Writelmm, R0 = 7, w = 1 as in wait state


// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking MOV Rn#<im8>, MOV R1, #2 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1101000100000010;                // MOV R0, #7 instruction encoded
sim_load = 1'b1;
sim_s = 1'b0;                                   // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait stat

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> Writelmm");
#10; 
output_checker(1'bx,1'bx,1'bx,`Writelmm,
                16'b0000000000000111,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Writelmm, R1 undefined, w = 0 as not in wait state
                                                     // R1 is undefined because of the delay of change in 'state', 
                                                     // causing 'readnum' change delay which is no longer on rising edge of clock
                                                     // Therefore R1 will be updated on next rising edge of clock

$display("Checking Writelmm -> Wait ... Checking R0 = 7, R1 = 2");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Writelmm, R0 = 7, R1 = 2, w = 1 as in wait state


// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking ADD Rd,Rn,Rm{,<sh_op>}, ADD R2, R1, R0, LSL#1 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1010000101001000;                // ADD R2, R1, R0,
sim_load = 1'b1;
sim_s = 1'b0;                                   // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait stat

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> GetA");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetA,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetA

$display("Checking GetA -> GetB");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetB,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, w = 1 as in wait state

$display("Checking GetB -> (ExecuteOperation) ADD");
#10; 
output_checker(1'bx,1'bx,1'bx,/*`ExecuteOperation,*/ `ADD,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, w = 1 as in wait state

$display("Checking (ExecuteOperation) ADD -> WriteReg");
#10; 
output_checker(1'bx,1'bx,1'bx,`WriteReg,
                16'b0000000000000111,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, w = 1 as in wait state

$display("Checking WriteReg -> Wait");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Wait, w = 1 as in wait state

// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking MOV Rd, Rm{,<sh_op>} : MOV R3, R2 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1100000001100010;                // MOV R3, R2
sim_load = 1'b1;
sim_s = 1'b0;                                 // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait stat

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> GetA");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetA,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetA
                                                    
$display("Checking GetA -> GetB");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetB,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, w = 1 as in wait state

$display("Checking GetB -> (ExecuteOperation) MOV_Rd_Rm");
#10; 
output_checker(1'bx,1'bx,1'bx,/*`ExecuteOperation,*/ `MOV_Rd_Rm,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in MOV_Rd_Rm

$display("Checking (ExecuteOperation) MOV_Rd_Rm -> WriteReg");
#10; 
output_checker(1'bx,1'bx,1'bx,`WriteReg,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in WriteReg

$display("Checking WriteReg -> Wait, R3 = R2 = 16");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Wait, w = 1 as in wait state


// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking AND Rd, Rn, Rm{,<sh_op>} : AND R4, R0, R1 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1011000010000001;                // AND R4, R0, R1
sim_load = 1'b1;
sim_s = 1'b0;                                 // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait state

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> GetA");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetA,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetA
                                                    
$display("Checking GetA -> GetB");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetB,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, 

$display("Checking GetB -> (ExecuteOperation) AND");
#10; 
output_checker(1'bx,1'bx,1'bx,/*`ExecuteOperation,*/ `AND,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in AND

$display("Checking (ExecuteOperation) AND -> WriteReg");
#10; 
output_checker(1'bx,1'bx,1'bx,`WriteReg,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in WriteReg

$display("Checking WriteReg -> Wait, R4 = R0 & R1 = 2");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Wait, w = 1 as in wait state


// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking MVN Rd, Rm{,<sh_op>} : MVN R5, R4 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1011100010100100;                // MVN R5, R4
sim_load = 1'b1;
sim_s = 1'b0;                                 // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait state

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> GetA");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetA,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetA
                                                    
$display("Checking GetA -> GetB");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetB,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, 

$display("Checking GetB -> (ExecuteOperation) MVN");
#10; 
output_checker(1'bx,1'bx,1'bx,/*`ExecuteOperation,*/ `MVN,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in MVN

$display("Checking (ExecuteOperation) MVN -> WriteReg");
#10; 
output_checker(1'bx,1'bx,1'bx,`WriteReg,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in WriteReg

$display("Checking WriteReg -> Wait, R5 = ~R4 = -3");
#10; 
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Wait, w = 1 as in wait state


// __________________________________________________________ NEW CHECK _________________________________________________________________

$display("--- Checking CMP Rn, Rm{,<sh_op>} : CMP R5, R4 instruction --- ");

$display("Checking input instruction encoding");
sim_in = 16'b1010110100000100;                // CMP R5, R4 instruction
sim_load = 1'b1;
sim_s = 1'b0;                                 // to stay in wait state
#10
output_checker(1'bx,1'bx,1'bx,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in wait , R0 undefined, w = 1 as in wait state

$display("Checking Wait -> Decode");
sim_s = 1'b1;
#10; 
output_checker(1'bx,1'bx,1'bx,`Decode,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in Decode, R0 undefined, w = 0 as not in wait state

$display("Checking Decode -> GetA");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetA,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetA
                                                    
$display("Checking GetA -> GetB");
#10; 
output_checker(1'bx,1'bx,1'bx,`GetB,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in GetB, 

$display("Checking GetB -> (ExecuteOperation) CMP");
#10; 
output_checker(1'bx,1'bx,1'bx,/*`ExecuteOperation,*/ `CMP,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b0); // State should be in CMP

$display("Checking (ExecuteOperation) CMP -> Wait"); // does not go to WriteReg state as we are not writing to register
#10; 
output_checker(1'b1,1'b0,1'b0,`Wait,
                16'b0000000000000111,16'b0000000000000010,16'b0000000000010000,16'b0000000000010000,16'b0000000000000010,16'b1111111111111101,16'bxxxxxxxxxxxxxxxx,16'bxxxxxxxxxxxxxxxx,
                1'b1); // State should be in Wait, w = 1 as in wait state
                       // N should be 1 as R5 - R4 is -ve


if (~err) $display("PASSED"); 
    else $display("FAILED");
    $stop;




end

endmodule